Jitter generation circuit and semiconductor device

ABSTRACT

A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

CROSS-REFERENCE TO RELATED APPLICATION

This is a Divisional Application which claims the benefit of pendingU.S. patent application Ser. No. 11/217,459, filed Sep. 2, 2005, whichin turn is a Divisional Application of application Ser. No. 10/743,188,filed Dec. 23, 2003, now U.S. Pat. No. 6,975,148 B2. The disclosures ofthe prior applications are hereby incorporated herein in their entiretyby reference.

BACKGROUND OF THE INVENTION

The present invention relates to a spread spectrum clock generationcircuit which generates a clock signal the period of which changesslightly in order to reduce electromagnetic wave radiation, a jittergeneration circuit which adds a jitter to a clock signal or the like,and a semiconductor device using the circuits.

Recently, as semiconductor devices have increased in speed and degree ofintegration, a problem of EMI (electromagnetic interference) due toelectromagnetic wave radiation from a device has attracted moreattention. As the operation frequency has increased, the wavelength hasbecome shorter and shorter, and the wiring length of a connectingcircuit, or inside the substrate, has become almost as short as thewavelength of a high frequency signal, therefore, the connectingsections of wires or the like may serve as antennas and electromagneticwave radiation is increased. The electromagnetic wave radiation ofelectronic devices using semiconductor devices which operate at a highclock frequency causes adverse effects such as malfunctions due tomutual interference between electronic device and interference withcommunication devices.

In order to solve these problems, measures are currently taken againstelectronic devices, which cause the problem of the electromagnetic waveradiation, in which the electromagnetic wave radiation is reduced byimproving the arrangement or the like of circuits, the leakage ofelectromagnetic waves is reduced by shielding the electromagnetic waves,and so on. However, as portable equipment or the like is required to bemore compact and lighter, a problem occurs in that it is difficult tosufficiently carry out the shielding in order to reduce theelectromagnetic wave radiation.

Therefore, often, the operating clock frequency of a semiconductordevice is changed slightly and/or the peak of noise is scattered by theaddition of a jitter to a clock signal.

In Japanese Unexamined Patent Publication (Kokai) No. 2000-101424, aspread spectrum clock generation (SSCG) circuit has been proposed, whichcarries out spread spectrum processing for slightly changing theoperating clock frequency of a semiconductor device.

FIG. 1 is a diagram showing a configuration example of a conventionalSSCG circuit. This example shows a circuit which generates a clock CKfrom a reference clock CLK, the frequency of the clock CK being M/Ntimes that of the reference clock CLK, by utilizing a PLL (Phase LockedLoop) circuit. This circuit consists of a 1/N divider 11, a frequencyphase comparator 12, a charge pump (CP) 13, a loop-filter 14, a voltagecontrol oscillator (VCO) 17, a 1/M divider 18, a modulator 15, and avoltage addition circuit 16. The frequency phase comparator 12 detects aphase difference between the CLK divided by a factor of N and the CKdivided by a factor of M and outputs a signal to control the CP 13 inaccordance with the phase difference. The CP 13 outputs a signal tocharge and discharge the loop-filter 14 in accordance with the phasedifference and a differential voltage in accordance with the phasedifference is generated at one end of the loop-filter 14. In aconventional clock generation circuit which does not carry out thespread spectrum modulation, the differential voltage is applied to theVCO 17 and a clock with a constant period is generated accordingly. Inthe SSCG circuit, however, the modulator 15 outputs a spectrummodulation signal which has a small amplitude and changes in apredetermined spread spectrum modulation period as shown in FIG. 2, andthe spectrum modulation signal is added to the differential voltage inthe voltage addition circuit 16 and applied to the VCO 17. An amplitudeof the spectrum modulation signal is sufficiently smaller than that ofthe differential signal and the spread spectrum modulation period issufficiently longer than a period of the generated clock CK. As aresult, the period of the generated clock CK changes in the apredetermined cycle, with the period M/N times the period of thereference clock CLK being the center. The coefficient of change ofperiod and the cycle are determined by the spectrum modulation signalgenerated by the modulator. The response time of the PLL circuit is setto a time sufficiently longer than the period of the spectrum modulationsignal.

U.S. Pat. No. 5,488,627 and Japanese Unexamined Patent Publication(Kokai) No. 9-98152 have suggested the use of a waveform as shown inFIG. 3 as a spectrum modulation signal. The use of this waveform makesthe peak lower and reduces the electromagnetic wave radiation.

Japanese Unexamined Patent Publication (Kokai) No. 8-292820 hasdisclosed a configuration in which the period of a spectrum modulationsignal is changed randomly. The electromagnetic wave radiation isreduced by randomly changing the period.

Japanese Unexamined Patent Publication (Kokai) No. 7-202652 hasdisclosed a clock pulse generator which adds a jitter to a clock signal.The clock pulse generator disclosed in Japanese Unexamined PatentPublication (Kokai) No. 7-202652 comprises a plurality of delay circuitsconnected in series and a multiplexer connected via a tap to the outputof each delay circuit. The clock signal to be input from each delaycircuit via the tap to the multiplexer becomes a signal delayed in phasewith respect to the reference phase respectively, and any one of signalsdelayed in phase is output selectively by controlling the multiplexer.

Moreover, Japanese Unexamined Patent Publication (Kokai) No. 11-110067has disclosed a semiconductor device in which the period of a clocksignal is constant and the peak value of the EMI intensity is reduced byscattering the EMI intensity to each frequency component by changing theduty ratio.

SUMMARY OF THE INVENTION

Generally, the spectrum modulation signal uses a triangular wave asshown in FIG. 2. In other words, the generated clock CK changes itsfrequency as shown in FIG. 2. When a triangular wave is used, however,as peaks occur at both ends of the width of the spectrum generated bythe spread, a problem occurs that the electromagnetic wave radiation atthis part is increased.

However, it is not easy to generate such a waveform as shown in FIG. 3,and the scale of a circuit which generates such a waveform becomeslarger, resulting in a problem of higher cost.

Moreover, if the period of a spectrum modulation signal is changedrandomly, there may be a case where the period of a generated clockchanges considerably in a short time. This is undesirable from thestandpoint of the operation of an SSCG circuit. When a generated clockis used in a logic circuit or the like, there is no operational problemif the rate of change with respect to time is small even though therange of change is large, but if the period suddenly changesconsiderably, a problem occurs that a normal operation is not secured.

In this clock pulse generator, a fixed delay time is set in accordancewith the delay circuit. A general semiconductor device is designed insuch a way that it can operate at different clock frequencies within apredetermined range. Therefore, when this clock pulse generator is used,a problem occurs that it is not possible to add a proper jitter inaccordance with the frequency, if the clock frequency is changed. Inaddition to the delay circuit, a multiplexer and a circuit to controlthe multiplexer are required for the clock pulse generator, therefore aproblem occurs that the circuit configuration becomes more complex.

The configuration in which the duty ratio is changed brings about aproblem that the range in which the spectrum of the EMI can be scatteredis narrow and that a sufficient effect of noise reduction cannot beobtained.

The first object of the present invention is to realize a spreadspectrum clock generation circuit capable of further reducing theelectromagnetic wave radiation with a simple configuration.

The second object of the present invention is to realize a jittergeneration circuit and a semiconductor device capable of adding a properjitter and efficiently reducing the radiation noise.

In order to realize the above-mentioned first object, a spread spectrumclock generation circuit according to a first aspect of the presentinvention is characterized in that a spread spectrum modulation circuitmodulates a differential signal and generates a spread spectrummodulation signal the period of which changes so as to be multipledifferent periods. It is desirable for the spread spectrum modulationsignal to change in period for each period in order.

FIG. 4 is a configuration diagram based on the principle of the spreadspectrum clock generation circuit according to the first aspect of thepresent invention. As shown in FIG. 4, the spread spectrum clockgeneration circuit of the present invention comprises the frequencyphase comparator 12 which detects the phase difference between thereference clock CLK and the generated clock CK, the charge pump 13 whichgenerates a charge/discharge signal in accordance with the detectedphase difference, the loop-filter 14 which generates a differentialsignal, a spread spectrum modulation circuit 19 which modulates thedifferential signal and generates a spread spectrum modulation signal,and a clock generator 20 which generates a generated clock having afrequency in accordance with the spread spectrum modulation signal, andis characterized in that the spread spectrum modulation circuit 19generates a spread spectrum modulation signal the period of whichchanges so as to take multiple different periods.

FIG. 5A and FIG. 5B are diagrams illustrating the principle of the firstaspect of the present invention. In a conventional SSCG circuit, atriangular wave shaped spread spectrum modulation signal which changesin a constant period as shown in FIG. 2 was added to a differentialsignal. Therefore, for example, if an oscillation frequency of 10 MHz ismodulated with 30 kHz, the spectrum components are spaced at intervalsof 30 kHz, that is, 9.91 MHz, 9.94 MHz, 9.97 MHz, 10.00 MHz, 10.03 MHz,10.06 MHz, 10.09 MHz, with 10 MHz being the center, as shown in FIG. 6A.In contrast to this, in the first aspect of the present invention, theperiod (frequency) of a spread spectrum modulation signal is changed insuch a way that tm1=30 kHz, tm2=27 kHz, and tm3=33 kHz, as shown in FIG.5A or FIG. 5B. In this case, as shown in FIG. 6B, the spectrumcomponents are divided into three groups, that is, one group in whichthey are spaced at intervals of 27 kHz, another group in which they arespaced at intervals of 30 kHz, and the other group in which they arespaced at intervals of 33 kHz, therefore, the height of each spectrum isreduced compared to the conventional case.

As described above, according to the first aspect of the presentinvention, as the period of the spread spectrum modulation signalchanges so as to take multiple different periods, the spectrum isfurther spread compared to the case where the period is constant,therefore, the electromagnetic wave radiation can be further reduced.Moreover, as the period of the spread spectrum modulation signal changesfor each period in order, the period is unlikely to change rapidly in ashort time and the cycle-to-cycle jitter, which is the difference inperiod between neighboring clock pulses, is small. Therefore, even whenthe generated clock is used in circuits such as a logic circuit, noproblem of circuit operation is brought about.

It is also possible to change the period of the spread spectrummodulation signal at the point of zero-crossing as shown in FIG. 5A, orchange the period at the point where the amplitude is minimum as shownin FIG. 5B.

There can be various cases of modification such as a case where theperiod is changed at the position of maximum amplitude and a case wherethe period is changed at the position where the amplitude reaches apredetermined value. Moreover, the number of variable periods is notlimited to three, but may be four or more as long as the number islarger than one.

As a clock generator, a voltage control oscillator (VCO) can be used.When a VCO is used as a clock generator, a spread spectrum modulationsignal is obtained by adding the spread spectrum modulation signalgenerated in the spread spectrum modulation circuit to the differentialvoltage produced at one end of the loop-filter, and the signal isapplied to the VCO.

When a VCO is used as a clock generator, the spread spectrum modulationcircuit can be realized by the use of an analog circuit or a digitalcircuit. When the spread spectrum modulation circuit is realized by theuse of an analog circuit, for example, a spread spectrum analog voltagesignal, the period of which changes so as to take multiple differentperiods, is generated in an analog modulator and the spread spectrumanalog voltage signal is added to a differential signal in a voltageaddition circuit. An analog modulator can be realized by comprising aplurality of different capacitors, a plurality of switches which selectone of the plurality of different capacitors, a constant current sourcewhich supplies a constant current to the selected capacitor or makes aconstant current flow out of the selected capacitor, a hysteresiscomparator which detects the fact that the voltage of the selectedcapacitor reaches a first and second predetermined voltages, and aswitch control circuit which switches the selection of a plurality ofswitches when the hysteresis comparator detects the fact that the firstand second predetermined voltages are reached.

Further, when the above circuits are used, a slope of an amplitude ofthe spread spectrum modulation is straight, and the slope of theamplitude change is determined by the selection of the switches.Therefore, when the selection of the switches is changed in apredetermined period of the spread spectrum modulation signal, a spreadspectrum modulation signal shown in FIG. 67 can be obtained. In otherwords, a spread spectrum modulation signal similar to that shown in FIG.3 can be obtained by a simple constitution.

When the spread spectrum modulation circuit is realized by the use of adigital circuit, an output code the period of which changes so as totake multiple different periods is generated in the digital controlcircuit, a spread spectrum voltage signal in accordance with the outputcode is generated in a digital-to-analog conversion voltage circuit, andthe spread spectrum voltage signal is added to a differential signal ina voltage addition circuit.

The present invention can be applied to a spread spectrum modulationcircuit which uses a current oscillator (ICO) instead of a VCO. Thisspread spectrum modulation circuit has a configuration in which adifferential voltage is converted into a differential current signal ina voltage-current conversion circuit, the differential current signal ismade to go through the spread spectrum modulation in a current variablecircuit, and the spread spectrum modulation signal is applied to thecurrent oscillator (ICO). When the present invention is applied to aspread spectrum modulation circuit which uses an ICO, a voltage-currentconversion circuit, which converts a differential voltage into adifferential current signal, is further comprised and an ICO is used asa clock generator. The spread spectrum modulation circuit comprises adigital control circuit which generates an output code the period ofwhich changes so as to take multiple different periods and a currentvariable circuit provided between the voltage-current conversion circuitand the ICO and which modulates a differential current signal inaccordance with the output code and generates a spread spectrum currentmodulation signal.

The current variable circuit can be realized by comprising a circuitwhich generates a differential current signal with a predetermined ratioand a digital-to-analog conversion current circuit which converts anoutput code into a spread spectrum current signal, which is an analogsignal, and adds it to the differential current signal with apredetermined ratio. It is desirable for the current variable circuit tofurther comprise a low-pass filter which removes a high frequencycomponent.

A digital control circuit can be realized by comprising a plurality ofdividers with a different dividing ratio which divides a clock, aswitching controller which selects the output of the plurality of thedivider in order, an up/down counter which counts the selected divingclock, and a counter which counts the dividing clock and switchesbetween the up operation and the down operation of the up/down counterfor each predetermined count number.

A digital control circuit can also be realized by the use of a computersystem which is controlled by programs.

When the spread spectrum modulation circuit is realized by the use of adigital circuit, the spread spectrum modulation signal shown in FIGS.5A, 5B and 67 can be easily obtained.

Moreover, in order to realize the above-mentioned first object, a spreadspectrum clock generation circuit according to a second aspect of thepresent invention is characterized in that a spread spectrum modulationcircuit modulates a differential signal and generates a spread spectrummodulation signal in which a local maximum and minimum of an amplitudechange. For example, the spread spectrum modulation signal has atriangular waveform and its amplitude or mean level in each cyclechanges.

The spread spectrum clock generation circuit according to the secondaspect also has a configuration as shown in FIG. 4 and the spreadspectrum modulation circuit 19 generates a spread spectrum modulationsignal in which a local maximum and minimum of an amplitude change.

FIG. 7A to FIG. 7D are diagrams illustrating the principle of the secondaspect of the present invention in which the amplitude changes. Theamplitude of the spread spectrum modulation signal is changed as shownin FIG. 7A. In this case, the spectrum component becomes one in whichboth ends are lowered as shown in FIG. 7D, which is a synthesizedspectrum of a spectrum whose amplitude is small, as shown in FIG. 7B,and a spectrum whose amplitude is large, as shown in FIG. 7C.

As described above, according to the second aspect of the presentinvention, as the amplitude of the spread spectrum modulation signalchanges so as to have multiple different periods, it is possible tolower both the ends of the spectrum than when the amplitude is constantand the electromagnetic wave radiation can be further reduced. It isdesirable for the amplitude of the spread spectrum modulation signal tochange without a sudden change between neighboring periods for eachperiod. For example, when the spread spectrum modulation signal changesso as to take positive and negative levels, with the zero level beingthe center, as shown in FIG. 7A, the amplitude is changed when thesignal is at the zero level. When the minimum level is constant, theamplitude is changed when the level is minimum. In this manner, thespread spectrum modulation signal does not change the level suddenly onthe way and the cycle-to-cycle jitter, the difference between theperiods of neighboring clock pulses is small. Therefore, there is noproblem of circuit operation even when the generated clock is used in alogic circuit or the like.

Although FIG. 7A shows a combination of two kinds of amplitudes, thatis, a large amplitude and a small amplitude, it is also possible tocombine three or more kinds of amplitudes. Further, the mean level ofthe signal can be shifted in each cycle as shown in FIG. 68. Further,combinations of the first and second aspects are also available. Forexample, the spread spectrum modulation signal can simultaneouslychanges its amplitude and/or mean level with the spread spectrummodulation cycle. FIG. 69 shows a waveform of the spread spectrummodulation signal in which the period and the mean level of the spreadspectrum modulation signal in each cycle are simultaneously changed. Inrespective cases, it is important that the amplitude continuouslychanges.

When a VCO is used as a clock generator, a spread spectrum modulationsignal is obtained by adding the spread spectrum modulation signalgenerated in a spread spectrum modulation circuit to a differentialvoltage generated at one end of a loop-filter, and the signal is appliedto the VCO.

When a VCO is used as a clock generator, a spread spectrum modulationcircuit can be realized by the use of an analog circuit or a digitalcircuit. When a spread spectrum modulation circuit is realized by theuse of an analog circuit, for example, a spread spectrum analog voltagesignal which changes so as to take multiple different amplitudes isgenerated in an analog modulator and the spread spectrum analog voltagesignal is added to the differential signal in a voltage additioncircuit. The analog modulator can be realized by comprising a capacitor,a constant current source which switches between one state in which thecapacitor is charged with a constant current and the other state inwhich a constant current is discharged from the capacitor, and aswitching control circuit which changes the switching cycle of theconstant current source.

When a spread spectrum modulation circuit is realized by a digitalcircuit, the spread spectrum modulation circuit can be realized by adigital control circuit which generates an output code which changescontinuously between the maximum value and the minimum value and atleast one of the maximum value and the minimum value changes so as totake multiple different values for each period in order, a voltagedigital-to-analog conversion circuit which generates a spread spectrummodulation voltage signal in accordance with the output code, and avoltage addition circuit which adds the spread spectrum voltage signalto a differential voltage.

It is also possible to apply the second aspect of the present inventionto a spread spectrum modulation circuit which uses the above-mentionedICO. In this case, the spread spectrum modulation circuit comprises adigital control circuit which generates an output code which changescontinuously between the maximum value and the minimum value and atleast one of the maximum value and the minimum value changes so as totake multiple different values for each period in order, and a currentvariable circuit which is provided between a voltage-current conversioncircuit and a current control oscillator and which generates a spreadspectrum current modulation signal by modulating a differential currentsignal in accordance with the output code.

A current variable circuit can be realized by a digital-to-analogconversion current circuit which converts an-output code into a spreadspectrum current signal, which is an analog signal, and adds it to adifferential current signal. It is desirable for the current variablecircuit to further comprise a low-pass filter which removes a highfrequency component.

The spread spectrum modulation circuit can be also realized by a digitalcontrol circuit which generates a spectrum modulation code the value ofwhich changes in order in a predetermined period and a level change codethe value of which changes so as to take multiple different values inorder for each predetermined period, a first current variable circuitwhich is provided between a voltage-current conversion circuit and acurrent control oscillator and which modulates a current signal with apredetermined ratio of a differential current signal in accordance witha spectrum modulation code, and a second current variable circuit whichamplifies the output of the first current variable circuit in accordancewith the level change code, and by adding the output of the secondcurrent variable circuit to the differential current signal. Moreover,it is possible to carry out the level change earlier in thisconfiguration, and in this case, the first current variable circuitamplifies the current signal with a predetermined ratio of thedifferential current signal in accordance with the level change code andthe second current variable circuit modulates the output of the firstcurrent variable circuit in accordance with the spectrum modulationcode.

A digital control circuit whose configuration is the same as that usedin the first aspect can be used and can also be realized by the use of acomputer system controlled by programs.

Moreover, a spread spectrum clock generation circuit according to athird aspect of the present invention in order to realize theabove-mentioned first object combines a spread spectrum modulationcircuit which carries out the spread spectrum modulation on a currentsignal in digital processing and an amplifier circuit.

It is desirable to change the waveform of the spread spectrum modulationin accordance with purposes, but the configuration of a current typedigital-to-analog converter (IDAC) making up a digital processing typespread spectrum modulation circuit is fixed in a chip and it isnecessary to use a large scale IDAC with a large number of bits in orderto provide a predetermined resolution for a wide range of amplitude, andas a result, the cost is increased. According to the third aspect of thepresent invention, it is possible to add a signal, which has gonethrough the spread spectrum modulation in an IDAC, to a differentialcurrent signal after the modulated signal is amplified to a properamplitude in an amplifier circuit, or to carry out the spread spectrummodulation in an IDAC on a differential current signal amplified to aproper amplitude, therefore, the resolution of the IDAC can always beutilized to the maximum. Because of this, it is possible to use a smallscale IDAC with a relatively small number of bits.

Moreover, a spread spectrum clock generation circuit according to afourth aspect of the present invention in order to realize theabove-mentioned first object is configured in such a way that a currentinjection circuit is connected to the connection node of a resistor anda capacitor making up a loop-filter, and the capacitor is charged anddischarged so that the voltage of the capacitor changes with a voltageamplitude smaller than the capacitor voltage in a period of the spreadspectrum modulation longer than the period of the generated clock.According to the fourth aspect of the present invention, it is possibleto carry out a spread spectrum modulation with a smooth change by theuse of a simple circuit.

Moreover, in a jitter generation circuit according to a fifth aspect ofthe present invention in order to realize the above-mentioned secondobject, the reversing timing of an output level is changed with respectto a constant interval timing in accordance with the period of thereference input signal by switching the threshold voltages of thecircuit. In this manner, an output signal, which is the reference inputsignal to which a jitter has been added, is output. In thisconfiguration, it is possible to add a jitter to the reference inputsignal with a simpler circuit configuration than that of the prior art.On the other hand, when the frequency of the reference input signalchanges, the jitter of the output signal changes in accordance with thefrequency of the reference input signal.

The jitter generation circuit according to the fifth aspect comprises ahysteresis inverter circuit having a hysteresis characteristic, aninverter circuit without a hysteresis characteristic, and a switchcircuit provided between an output terminal and the hysteresis invertercircuit and between the output terminal and the inverter circuit,respectively, and the jitter generation circuit is configured in such away that either the hysteresis inverter circuit or the inverter circuitis connected to the output terminal by the use of the switch circuit. Inthis manner, the threshold voltages are switched and a jitter can begenerated in an output signal.

Moreover, the jitter generation circuit according to the fifth aspect isconfigured so as to comprise a hysteresis inverter circuit consisting ofa plurality of transistors and a switch to cut off the transistors,which are provided to make the hysteresis inverter circuit havehysteresis, from the hysteresis inverter circuit. In this manner, thethreshold voltages are switched and it becomes possible to generate ajitter in an output signal.

The jitter generation circuit according to the fifth aspect is alsoconfigured in such a way that a plurality of gate circuits, whosethreshold voltages are different, are connected in parallel and any oneof the gate circuits is selectively connected to an output terminal bythe use of a switch circuit provided between the output terminal tooutput an output signal and each gate circuit, respectively. In thismanner, the threshold voltages are switched and it becomes possible togenerate a jitter in an output signal.

In a semiconductor device using the jitter generation circuit accordingto the fifth aspect of the present invention, an output signal to whicha jitter has been added is output from the jitter generation circuit andan internal circuit is operated based on the output signal, therefore,the radiation noise produced during operation of the internal circuit isreduced effectively. When the generated clock signal changes in arectangular wave manner in such a semiconductor device, a circuit isprovided which changes a clock signal into a sinusoidal wave signal. Aselection signal, which switches the threshold voltages, is generatedfrom the clock signal.

Moreover, when the internal circuit in the semiconductor device can beclassified into a plurality of groups whose operation frequency isdifferent, a plurality of jitter generation circuits which add adifferent amount of jitter are provided to supply a jitter to eachcircuit group in accordance with the operation frequency. It is alsopossible to supply a clock signal, to which a jitter is not added, to acircuit group whose operation timing is strict and whose operationfrequency is high. In this manner, as it is possible to adjust theamount of jitter in accordance with the operation frequency, the speedof the circuit operation can be increased and at the same time theradiation noise can be reduced. In this case, the jitter generationcircuit can be one according to the fifth aspect of the presentinvention or to another one.

In this case, a dividing circuit is provided in order to generate clocksignals with a different frequency and they are supplied to each jittergeneration circuit.

Moreover, it is possible to make adjustable the amount of jitter to beadded to a clock signal in accordance with the operation state of theinternal circuit, for example, the power supply voltage supplied to theinternal circuit or the operation speed of the internal circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the invention will be more clearlyunderstood from the following description taken in conjunction with theaccompanying drawings, wherein:

FIG. 1 is a diagram showing a configuration example of a conventionalspread spectrum clock generation (SSCG) circuit;

FIG. 2 is a diagram showing a modulator output (spread spectrummodulation signal) in a conventional case;

FIG. 3 is a diagram showing another example of a modulator output(spread spectrum modulation signal) in a conventional case;

FIG. 4 is a diagram showing a configuration based on the principle infirst and second aspects;

FIG. 5A and FIG. 5B are diagrams illustrating the principle of the firstaspect of the present invention and showing an example of a spreadspectrum modulation signal of the present invention;

FIG. 6A and FIG. 6B are diagrams showing how the spectrum is improvedwhen the first aspect of the present invention is applied;

FIG. 7A and FIG. 7B are diagrams illustrating the principle of thesecond aspect of the present invention and showing an example of thespread spectrum modulation signal of the present invention;

FIG. 8 is a diagram showing the configuration of an SSCG according to afirst embodiment of the present invention;

FIG. 9 is a diagram showing the output of a control circuit (change incode) in the first embodiment;

FIG. 10 is a diagram showing the configuration of an SSCG according to asecond embodiment of the present invention;

FIG. 11 is a diagram showing the circuit configuration of an analogmodulation circuit in the second embodiment;

FIG. 12 is a diagram showing the operation of the analog modulationcircuit in the second embodiment;

FIG. 13 is a diagram showing the configuration of an SSCG according to athird embodiment of the present invention;

FIG. 14 is a diagram showing the circuit configuration of a frequencyphase comparator;

FIG. 15 is a diagram showing the circuit configuration of a charge pumpcircuit;

FIG. 16 is a diagram showing the circuit configuration of avoltage-current conversion (V-I conversion) circuit;

FIG. 17 is a diagram showing the circuit configuration of a currentcontrol oscillation circuit (ICO);

FIG. 18 is a diagram showing the configuration circuit of a currentdigital-to-analog converter (IDAC);

FIG. 19 is a diagram showing the configuration of a control circuit inthe third embodiment;

FIG. 20 is a diagram illustrating the generation of a dividing clock inthe control circuit in the third embodiment;

FIG. 21 is a diagram showing the operation of an up/down counter in thecontrol circuit in the third embodiment;

FIG. 22 is a diagram showing the circuit configuration of an SSCG in afourth embodiment of the present invention;

FIG. 23 is a diagram showing the circuit configuration of an IDAC with alow-pass filter;

FIG. 24 is a diagram showing an output of a control circuit (change incode) in a fifth embodiment of the present invention;

FIG. 25A and FIG. 25B are diagrams showing the configuration andoperation for realizing the control circuit in the fifth embodiment bythe use of a logic circuit;

FIG. 26A and FIG. 26B are diagrams showing the configuration andoperation of an SSCG in a sixth embodiment of the present invention;

FIG. 27 is a diagram showing the circuit configuration and operation ofan analog modulation circuit in a seventh embodiment of the presentinvention;

FIG. 28 is a diagram showing the circuit configuration of a first IDACin the seventh embodiment;

FIG. 29 is a diagram showing the circuit configuration of a second IDACin the seventh embodiment;

FIG. 30A to FIG. 30C are diagrams illustrating the problem when theamplitude is changed by the use of the IDAC;

FIG. 31A and FIG. 31B are diagrams showing the configuration based onthe principle of a third aspect of the present invention;

FIG. 32A and FIG. 32B are diagrams illustrating the principle of thethird aspect of the present invention;

FIG. 33 is a diagram showing the configuration of an SSCG in an eightembodiment of the present invention;

FIG. 34 and FIG. 34B are diagrams showing the configuration andoperation for realizing a pattern control circuit in the eighthembodiment by the use of a logic circuit;

FIG. 35 is a diagram showing the configuration of an SSCG in a ninthembodiment of the present invention;

FIG. 36A to FIG. 36C are diagrams showing examples of a modulatedwaveform when the IDAC is used;

FIG. 37 is a diagram showing the basic configuration of a spreadspectrum clock generation (SSCG) according to a fourth aspect of thepresent invention;

FIG. 38 is a diagram showing the basic configuration of a currentinjection circuit used in the fourth aspect;

FIG. 39 is a diagram showing the basic configuration of an SSCG circuitin a tenth embodiment of the present invention;

FIG. 40 is a diagram showing the configuration of a reference currentsource circuit;

FIG. 41 is a diagram showing the configuration of a current sourcecontrol circuit;

FIG. 42 is a diagram showing the configuration of a current sourcecircuit;

FIG. 43A to FIG. 43D are diagrams showing the operation waveforms of acurrent source control signal, a current source output current and a VCOinput voltage;

FIG. 44 is a diagram showing the circuit configuration of an SSCGcircuit in an eleventh embodiment of the present invention;

FIG. 45 is a diagram showing the circuit configuration of an SSCGcircuit in a twelfth embodiment of the present invention;

FIG. 46 is a diagram showing the circuit configuration of an SSCGcircuit in a thirteenth embodiment of the present invention;

FIG. 47 is a diagram showing the circuit configuration of an SSCGcircuit in a fourteenth embodiment of the present invention;

FIG. 48 is a diagram showing the circuit configuration of a push-pulltype IDAC used in the SSCG circuit in the fourteenth embodiment;

FIG. 49A to FIG. 49C are diagrams illustrating the operation of apush-pull type IDAC in the fourteenth embodiment;

FIG. 50 is a diagram showing the circuit configuration of an SSCGcircuit in a fifteenth embodiment of the present invention;

FIG. 51 is a diagram showing the circuit configuration of an SSCGcircuit in a sixteenth embodiment of the present invention;

FIG. 52 is a diagram showing the circuit configuration of an SSCGcircuit in a seventeenth embodiment of the present invention;

FIG. 53 is a diagram showing the configuration of a semiconductor devicein an eighteenth embodiment of the present invention;

FIG. 54 is an operation waveform chart of a jitter generation circuit inthe eighteenth embodiment;

FIG. 55 is a diagram showing the configuration of a jitter generationcircuit in a nineteenth embodiment of the present invention;

FIG. 56 is an operation waveform chart of the jitter generation circuitin the nineteenth embodiment;

FIG. 57 is a diagram showing another configuration example of the jittergeneration circuit;

FIG. 58 is a diagram showing another configuration example of the jittergeneration circuit;

FIG. 59 is a diagram showing a CR circuit;

FIG. 60 is a diagram showing the configuration of a conventionalsemiconductor device using the jitter generation circuit;

FIG. 61 is a diagram showing the configuration of a semiconductor devicein a twentieth embodiment of the present invention;

FIG. 62 is a diagram showing the configuration of a semiconductor devicein a twenty-first embodiment of the present invention;

FIG. 63 is a diagram showing the configuration of a semiconductor devicein a twenty-second embodiment of the present invention;

FIG. 64 is a diagram showing another configuration example of asemiconductor device;

FIG. 65 is a diagram showing another configuration example of asemiconductor device; and

FIG. 66 is a diagram showing another configuration example of asemiconductor device;

FIG. 67 is a diagram showing an example of a spread spectrum modulationsignal of the present invention;

FIG. 68 is a diagram showing an example of a spread spectrum modulationsignal of the present invention; and

FIG. 69 is a diagram showing an example of a spread spectrum modulationsignal of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 8 is a diagram showing the configuration of the spread spectrumclock generation (SSCG) circuit in the first embodiment of the presentinvention. As shown schematically, this circuit is a circuit in which aclock CK M/N times the reference clock CLK is generated therefrom by theuse of a PLL circuit as in the circuit shown in FIG. 1 but differs froma conventional one in that the period of a spread spectrum modulationsignal generated by a modulator 22 changes in order as shown in FIG. 5A.

As shown in FIG. 8, in the SSCG circuit in the first embodiment, acontrol circuit 21 generates an output code such as shown in FIG. 9 andoutputs it to the modulator 22. The modulator 22 is a voltagedigital-to-analog converter (VDAC) and converts the output code into ananalog voltage signal. In this manner, a spread spectrum modulationanalog voltage signal as shown in FIG. 5A is obtained. When the voltagesignal does not change smoothly because of the voltage change widthcorresponding to the least significant bit of the output code, alow-pass filter is used for smoothing. The voltage addition circuit 16adds the spread spectrum modulation analog voltage signal to adifferential voltage generated at one end of the loop-filter 14. In thismanner, the voltage to be applied to the VCO 17 changes with a smallamplitude while the period is changing in order, and the frequency(period) of a clock CK generated by the VCO 17 changes in a small rangein a predetermined period and, moreover, the period of change changes inorder.

It is possible to realize the control circuit 21 by the use of a digitallogic circuit or the like if it is not necessary to change the outputcode to be generated. The description will not given here because anyperson skilled in this field can devise such a circuit configurationeasily. It is also possible to realize the control circuit 21 by the useof a computer system controlled by programs such as a micro computer ora DSP. In this case, it is also possible to change the output code inaccordance with the external control.

FIG. 10 is a diagram showing the configuration of the SSCG circuit inthe second embodiment of the present invention. Although the spreadspectrum modulation analog voltage signal is generated by digitalprocessing in the first embodiment, the spread spectrum modulationanalog voltage signal is generated by analog processing in the secondembodiment.

FIG. 11 is a diagram showing the circuit configuration of a switchcontrol circuit 31 and an analog modulator 32 shown in FIG. 10, and FIG.12 is a diagram showing the operation of the analog modulator. As shownin FIG. 11, three capacitor elements C1 to C3 having a differentcapacitance are provided in this circuit and one end of each capacitorelement is connected to the ground and the other end is connectedcommonly via switches S1 to S3, respectively. The state of conduction orthe state of no conduction of each switch is controlled by the controlcircuit 31. The portion denoted by reference number 33 is a currentsource circuit which supplies (charges) a current equal to a current Iwhich flows in a constant current circuit to a terminal to which theswitches S1 to S3 are commonly connected or makes the current to flowout (discharge) from the terminal by the use of a current mirrorcircuit. The terminal to which the switches S1 to S3 are commonlyconnected is an output terminal of the analog modulator and connected toa hysteresis comparator 34. The hysteresis comparator 34 compares theinput voltage of the terminal to which the switches S1 to S3 arecommonly connected with first and second reference values and controlstransistors Tr1 and Tr2 of the current source circuit in accordance withthe comparison result, and switches the current source circuit betweenthe state of charging and the state of discharging.

The operation of the circuit shown in FIG. 11 is described below byreferring to FIG. 12.

First, the output of the hysteresis comparator 34 becomes “High (H)”,the transistor Tr1 is set to the state of conduction, Tr2 is set to thestate of no conduction, and the current source circuit is set to thestate of charging. The switch control circuit 31 outputs a selectionsignal which brings S1 into the state of conduction and S2 and S3, intothe state of no conduction. In this manner, the current I is supplied toC1 and the voltage of the analog modulator output increases. When thevoltage of the analog modulation output reaches a first predeterminedvalue, the output of the hysteresis comparator 34 changes to “Low (L)”Tr1 is set to the state of out of conduction, Tr2 is set to the state ofconduction, and the current source circuit is set to the state ofcharging. The change in the output of the hysteresis comparator 34 isalso notified to the switch control circuit 31. Because of this, thecurrent I flows out from C1 and voltage of the analog modulation outputdecreases.

When the voltage of the analog modulator output reaches a secondpredetermined value, the output of the hysteresis comparator 34 changesto “H”, Tr1 is set to the state of conduction, Tr2 is set to the stateof out of conduction, and the current source circuit is set to the stateof charging. The switch control circuit 31 switches S1 into the state ofout of conduction and S2, into the state of conduction in accordancewith the change in the output of the hysteresis comparator 34. S3remains in the state of out of conduction. Because of this, as the caseof C1, charging of C2 starts and, when voltage of the analog modulatoroutput reaches the first predetermined value, the output of thehysteresis comparator 34 changes to “L”, and the current source circuitis set to the state of charging. Then, the voltage of the analogmodulator output reaches the second predetermined value.

As the capacitance of C1 is different from that of C2, the timesrequired for charging and discharging differ and, therefore, triangularwaves with a different period are obtained. The similar operation isrepeated for C3. In this manner, the three analog modulator outputs withan identical amplitude but a different period, as shown in FIG. 11, areobtained.

Although a case where three capacitor elements are used is describedhere, it is also possible to use four or more capacitor elements, and toutilize the sum of capacitance values of a plurality of capacitorelements to generate angular waves with a different period bycontrolling two or more switches so that they are brought into the stateof conduction at the same time.

FIG. 13 is a diagram showing the configuration of the SSCG circuit inthe third embodiment of the present invention, which is an embodiment inwhich the present invention is applied to the configuration disclosed inthe above-mentioned Japanese Patent Application No. 2002-266631. Asshown in FIG. 13, the configuration is similar to that of the circuit inthe first embodiment shown in FIG. 8, but differs in that the voltageaddition circuit 16, the VCO 17, the control circuit 21 and themodulator (VDAC) 22 are replaced with a current oscillation circuit 41consisting of a voltage-current conversion (V-I conversion) circuit 42,a current digital-to-analog converter (IDAC) 43 and a current oscillator(ICO) 44. The current oscillation circuit 41 is controlled by a controlcircuit 45. The V-I conversion circuit 42 converts the terminal voltage(differential voltage) of the loop-filter 14 into a differential currentsignal. The IDAC 43, which corresponds to a current variable circuit,carries out the spread spectrum modulation on the differential currentsignal in accordance with the output code from the control circuit 45and applies the modulated spread spectrum modulation current signal tothe current oscillator (ICO) 44.

FIG. 14 is a diagram showing the circuit configuration of the frequencyphase comparator and FIG. 15 is a diagram showing the configuration ofthe charge pump 13. These circuits can be used in the first to thirdembodiments. As these circuits are widely known, no description will begiven here.

FIG. 16 shows the circuit configuration of a V-I conversion circuit tobe used in the third embodiment, FIG. 17 shows the configuration of anICO circuit to be used in the third embodiment, and FIG. 18 shows thecircuit configuration of an IDAC circuit to be used in the thirdembodiment.

FIG. 19 shows the configuration of the control circuit 14. As shownschematically, the control circuit 41 comprises three dividers 51 to 53which divide a control clock by different dividing ratios (1/9, 1/10,and 1/11 here), switches 55 to 57 which select an output of any one ofthe dividers, a switching control portion 54 which selects a switch, anup/down counter 58 which counts a selected dividing clock, and adividing counter 59 which controls the up/down counter 58. The up/downcounter 58 outputs a count value in an n-bit binary code.

FIG. 20 is a diagram showing the operation of the switching controlportion 54 and the divider. The dividers 51 to 53 output three kinds ofdividing clocks, each being a control clock divided with each dividingratio, respectively. As shown in FIG. 20, the switching control portion54 selects the switch 55 so as to bring the switch 55 into the state ofconduction while counting the control clock up to 9×16 clock. Therefore,the 1/9 dividing clock is output in the meantime. After counting thecontrol clock up to 9×16 clock, the switching control portion 54 bringsthe switch 56 into the state of conduction while counting the controlclock up to 10×16 clock, then while counting the control clock up to11×16 clock, the switching control portion 54 brings the switch 57 intothe state of conduction, and thus repeats the same operation. In thismanner, the up/down counter 58 and the dividing counter 59 are suppliedwith the 1/9 dividing clock, the 1/10 dividing clock, and the 1/11dividing clock in this order.

FIG. 21 is a diagram showing the operation of the up/down counter 58 andthe dividing counter 59. The dividing counter counts a selected dividingclock and when the count value reaches a predetermined value, the upcount operation and the down count operation of the up/down counter 58are switched, and this operation is repeated. FIG. 21 shows an examplein which the up count operation and the down count operation areswitched when counted up to eight. When the output code such as shown inFIG. 9 is generated, the operations are switched each time when countedup to 14. The up/down counter 58 counts the selected dividing clock andoutputs the count value in an n-bit binary code. As described above,because the period of the dividing clock to be supplied changes, thelength of one cycle (period) of the code output to be generated differsaccordingly. The code output from the up/down counter 58 is applied tothe IDAC 43.

As shown in FIG. 18, the IDAC 43 comprises a current mirror circuitconsisting of transistors TR11 to TR15, Tr20, and Tr30 to Tr3 n. Bysetting the size of the transistors properly as shown schematically, 90%of a current Iref output from the V-I conversion circuit 42 flowsthrough Tr20, 10% of the Iref flows through Tr3 n, (20×1/2^(n−2)) % ofthe Iref flows through Tr32, (20×1/2^(n−1)) % of the Iref flows throughTr31, and (20×1/2^(n)) % of the Iref flows through Tr30. When Tr4 n toTr40 are brought into the state of conduction by bit data /D0 to /Dn ofthe output code, a current passing through the corresponding Tr3 n toTr30 flows. Therefore, when all of the Tr4 n to Tr40 are brought intothe state of no conduction, an amount of current of 90% of the Irefwhich flows through Tr20 is output, and when all of the Tr4 n to Tr40are brought into the state of conduction, a current which passes throughthe Tr3 n to Tr30 flows in addition to the amount of current of 90% ofthe Iref which flows through the Tr20, and as a result, an amount ofcurrent of about 110% of the Iref is output. In other words, by settingthe bit data /D0 to /Dn of the output code to proper values, a properamount of current of about 90% to 110% of Iref is output as a result.

Therefore, by applying the output code of the up/down counter 58, whichchanges in such a way as shown in FIG. 21, to the IDAC 43 shown in FIG.18, it is possible to change the Iref in nine steps in increments ofabout 2.5% from 90% to about 110%, and at the same time, the period ofchange changes in three steps. In accordance with this, the ICO 44repeatedly increases and decreases the frequency (period) in incrementsand decrements of about 2.5% in a range of ±10%, and generates a clockCK the period of change of which changes. When an output code, whichchanges in such a way as shown in FIG. 9, is used, a signal whichchanges in fifteen steps in increments of about 1.4% can be obtained.

FIG. 22 is a diagram showing the configuration of the SSCG circuit inthe fourth embodiment of the present invention. The SSCG circuit in thefourth embodiment differs from that in the third embodiment in that thecontrol circuit 45 in the third embodiment is composed of a microcomputer or a DSP, a code as-shown in FIG. 8 is generated, and an IDACwith a low-pass filter as shown in FIG. 23 is used instead of the IDAC.

When a computer system, controlled by programs, such as a microcomputeror a DSP is used, it is possible to easily generate a code as shown inFIG. 8. Moreover, if the computer system has a sufficient capacity ofmemory and is capable of generating many codes, it is also possible toselect a code to be output in accordance with the condition of use.Still moreover, it is also possible to rewrite programs to output adesired code in accordance with the condition of use.

The IDAC shown in FIG. 23 is a circuit, in which a low-pass filter (LPF)consisting of a resistor R and a capacitor C is provided at the currentoutput portion of the IDAC shown in FIG. 17 and the output thereof isfurther output from a current mirror circuit. Thanks to this circuit, itis possible to smooth the change in the output current caused by thechange in the least significant bit /Dn of the output code and reduce aglitch (noise). If a current signal with a glitch is supplied to theIOC, the IOC outputs a high frequency signal in accordance with theglitch. Because of this, PLL is brought out of the locked state and aproblem arises that focusing to the reference frequency cannot beattained, but if an IDAC with LPF is used, such a problem can beavoided.

In the first through fourth embodiments, the period of the spreadspectrum modulation signal is changed when the value resides at a meanlevel as shown in FIG. 5A. However, the period of the spread spectrummodulation signal can be changed when the value resides at the maximumor minimum as shown in FIG. 5B. For example, in the circuit constitutionshown in FIG. 11, the switches are switched when the analog modulatedoutput becomes the first or second predetermined value, then, the spreadspectrum modulation signal shown in FIG. 5B can be obtained. Further, itis apparent that the spread spectrum modulation signal shown in FIG. 5Bcan be easily obtained in the first, third and fourth embodiments.Further, it is apparent that the spread spectrum modulation signal shownin FIG. 67 can be also obtained in the first, third and fourthembodiments.

The spread spectrum clock generation (SSCG) circuit, which will bedescribed below, in the fifth embodiment of the present invention has aconfiguration similar to the SSCG circuit in the first embodiment shownin FIG. 8, but differs from that in the first embodiment in that theamplitude of the spread spectrum modulation signal generated by themodulator 22 changes in order as shown in FIG. 7A.

In the SSCG circuit in the fifth embodiment, the control circuit 21generates an output code as shown in FIG. 24 and outputs it to themodulator 22. In the first period, the value of this output codeincreases from the middle value to the first maximum value and decreasesto the first minimum value, and then increases again. The period entersthe second period when the middle value is reached, and after the valueincreases from the middle value to the second maximum value, itdecreases to the second minimum value, and then increases again. Whenthe middle value is reached, the period enters the first period again,and the same operation is repeated. In this example, the length of oneperiod of the first period is different from that of the second period.If the voltage signal does not change smoothly because of the voltagechange width corresponding to the least significant bit of the outputcode, a low-pass filter is used for smoothing. In this manner, thevoltage to be applied to the VCO 17 changes with a small amplitude andthe amplitude and the period change for each period. Therefore, thefrequency (period) of a clock CK generated by the VCO 17 changescontinuously in a small range in each period and the maximum value andthe minimum value of the frequency in the period change for each period.Moreover, the period itself changes as a result.

The control circuit 21 can be realized by a computer system, controlledby programs, such as a microcomputer and a DSP, and in such a case, itis possible to change an output code in accordance with the externalcontrol.

The control circuit 21 can be realized by a digital logic circuit or thelike. FIG. 25A and FIG. 25B are diagrams showing the configuration andthe operation of the control circuit 21 realized by a digital logiccircuit. As shown in FIG. 25A, the control circuit 21 comprises anup/down counter 60 which counts a clock and a switching counter 61 whichcontrols the up/down counter 60. The up/down counter 60 outputs a countvalue in an n-bit binary code. As shown in FIG. 25B, the switchingcounter 61 counts a clock and when the count value reaches apredetermined value, the up count operation and the down count operationof the up/down counter 60 are switched and the predetermined value ischanged to 13, 14, 13 and 12 in this order, and this operation isrepeated afterward. In this manner, an output code which changes in sucha way as shown in FIG. 7 is obtained. It is desirable for the minimumvalue of the count value to be output as a control output to be zero,but this value can be arbitrary and not particularly limited. Forexample, it is possible to alternately repeat the first period in whichthe minimum value is zero and the maximum value is 15 and the secondperiod in which the minimum value is one and the maximum value is 14,but the value can be arbitrary and it is also possible to alternatelyrepeat, for example, the first period in which the minimum value is fiveand the maximum value is 30 and the second period in which the minimumvalue is seven and the maximum value is 28.

The voltage level output by the modulator 22 in accordance with a codeis adjusted with respect to the differential voltage generated at oneend of the loop-filter 14 in accordance with the coefficient of changeof the spread spectrum modulation.

FIG. 26A is a diagram showing the configuration of the analog modulatorin the SSCG circuit in the sixth embodiment of the present invention,and FIG. 26B is a diagram showing the operation of the analog modulator.The spread spectrum modulation analog voltage signal is generated bydigital processing in the fifth embodiment, but in the sixth embodiment,the spread spectrum modulation analog voltage signal is generated byanalog processing.

As shown in FIG. 26A, this circuit is provided with a capacitor elementwhose capacitance value is C1 and one end of the capacitor element isconnected to the ground. The portion denoted by reference number 36 is acurrent source circuit which supplies (charges) to or extracts(discharges) from the capacitor a current equal to the current I whichflows through the constant current circuit by the use of a currentmirror circuit, as the analog modulator in FIG. 11, and charging anddischarging are switched by the control of a switch control circuit 35.When the current source circuit is brought into the state of chargingthe capacitor is charged with the current I and the voltage at the endof the capacitor (analog modulator output voltage) increases. Then, whenthe current source circuit is brought into the state of discharging, thecurrent I is discharged from the capacitor and the analog modulatoroutput voltage decreases. As the capacitance value and the current valueare constant, if the charging time and the discharging time are changed,the maximum voltage and the minimum voltage change accordingly. As shownin FIG. 26B, when the voltage reaches the middle value while it isincreasing, if charging is carried out for a charging time t1 whichcorresponds to ¼ the period, the voltage reaches a maximum voltage VH1.Then, if discharging is carried out for a discharging time 2t1, thevoltage reaches a minimum voltage VL1. Next, if charging is carried outfor the charging time t1, the voltage reaches the middle voltage. Afterthis, if charging is carried out for a charging time t2, which isshorter than t1, the voltage reaches a maximum voltage VH2, which issmaller than VH1. Then, if discharging is carried out for a chargingtime 2t2, the voltage reaches a minimum voltage VL2, which is higherthan VL1. Finally, if charging is carried out for the charging time t2,the voltage reaches the middle voltage. The same operation is repeated.

In this manner, the spread spectrum voltage signal whose amplitudechanges for each period is obtained. In the second embodiment also, boththe amplitude and the period of the spread spectrum voltage signalchange. In order to generate a spread spectrum voltage signal only theamplitude of which changes and the period of which does not change, aconstant current source capable of charging or discharging withdifferent currents is provided in the circuit shown in FIG. 26A and thecurrent to be supplied is switched for each period. In this case, theswitch control circuit 35 switches the power supply between charging anddischarging in a predetermined period.

Further, the spread spectrum modulation signal shown in FIG. 67 can bealso obtained in the above circuit. In this case, the current to besupplied is switched in each cycle.

Although a case of switching between two amplitudes is shown here, it isalso possible to switch among three or more amplitudes.

As described above, the SSCG circuit in the fifth and sixth embodimentshas a configuration similar to that in the first and second embodiments,in which the amplitude of the spread spectrum modulation signal changes.It is also possible to change the amplitude of the spread spectrummodulation signal by the use of the SSCG circuit in the third and fourthembodiments. As it is easy for any engineer skilled in this field tounderstand the configuration and operation in this case, a detaileddescription will not be given here. It is also possible to change onlythe amplitude without changing the period if an IDAC having a resolutionwith a large number of bits is used.

In the fifth and sixth embodiments, the switching of the amplitude iscarried out when the signal value crosses the reference level as shownin FIG. 7A. However, it is also possible that a local maximum and/or alocal minimum of the value of the spread spectrum modulation signal ineach cycle change. For example, in the circuit shown in FIG. 25A, thepredetermined values for switching the up and down operations areshifted in one direction (increased or decreased) and the spreadspectrum modulation signal shown in FIG. 68 is obtained. In other words,a spread spectrum modulation signal of which mean level in each cycle isshifted can be obtained. Further, a spread spectrum modulation signal inwhich the local maximum and/or the local minimum of the signal valuechange can be obtained by changing the switching timing of the circuitshown in FIG. 26A. It is also apparent that such spread spectrummodulation signal can be easily obtained by the digital controlledmodulator.

Further, a spread spectrum modulation signal in which both of the localmaximum and/or the local minimum of the signal value and the periodchange can be obtained by combinations of the above-mentioned circuits.It is also apparent that such spread spectrum modulation signal can beeasily obtained by the digital controlled modulator.

FIG. 27 is a diagram showing the configuration of the SSCG circuit inthe seventh embodiment of the present invention. In the fifth and sixthembodiments, the period as well as the amplitude of the spread spectrummodulation signal is changed. Although it is also possible to changeonly the amplitude without changing the period by the use of theabove-mentioned IDAC with high resolution, in the seventh embodiment,only the amplitude is changed without changing the period by the use ofanother method.

As shown in FIG. 27, in the SSCG in the seventh embodiment, when theamplitude is changed by the use of the SSCG circuit in the fourthembodiment, a first IDAC 63, a second IDAC 64 and a control circuit forcontrolling these IDACs are provided and a signal, which has branchedoff from the output of the V-I conversion circuit 42 and gone throughthe spread spectrum modulation, is added to the output of the originalV-I conversion circuit 42 and applied to the ICO 44.

FIG. 28 is a diagram showing the configuration of the first IDAC 63, andFIG. 29 is a diagram showing the configuration of the second IDAC 64.The first IDAC 63 is modified from the IDAC shown in FIG. 18 byeliminating TR12, TR14 and Tr20 and setting the Tr size ratio of TR13 toX, and the current input Iref can be controlled in a range from zero toIref (1-½^(n))/X with n bits. Similarly, the second IDAC 64 can controlthe current input Iref in a range from Iref/(2 ^(m)Y) to Iref/Y with mbits. As a result, it is possible to carry out amplification with anarbitrary amplification factor in this range by setting Y and an m-bitcode properly.

In the seventh embodiment, in accordance with the control code outputfrom the control circuit 65, the first IDAC 63 carries out the spreadspectrum modulation on the current of 1/X Iref with a fixed amplitudeand period as conventionally. The second IDAC 64 carries outamplification with a fixed amplification factor during one period of thespread spectrum modulation and changes the amplification factor when theperiod changes. In this manner, a spread spectrum modulation signal, theperiod of which is constant and only the amplitude of which changes foreach period, is obtained. This spread spectrum modulation signal isadded to Iref from the V-I conversion circuit 42 (this is done only byconnecting a signal line) and applied to the ICO 44.

It is also possible to reverse the arrangement of the first IDAC 63 andthe second IDAC 64, and first carry out amplification by changing theamplification factor for each period and then carry out the spreadspectrum modulation on the amplified current signal.

As described above, in the SSCG circuit in the first to seventhembodiments, it is possible to realize a spread spectrum clockgeneration circuit capable of an excellent spread spectrum modulationwith a simple configuration.

The SSCG circuit using the above-mentioned IDAC is characterized in thatthe configuration of the addition circuit or the like is simple, thechange of the oscillation frequency can be controlled in a digitalmanner, and the control is precise and easy. The IDAC shown in FIG. 18can control the amount of current to be output by dividing about 20% ofthe range of change into n bits. In other words, the minimum resolutionis 20/2^(n) %. For example, when n=9, 2⁹=512 and the resolution is0.04%, which is obtained by dividing 20% into 500 steps, and the outputcurrent can be controlled with a 0.04% pitch from 80% to 100%.

Generally, the SSCG circuit is used in a form of a chip or a chip intowhich other circuits are integrated together. It is necessary for theSSCG circuit which carries out the spread spectrum modulation to changethe amplitude of the spread spectrum modulation in accordance with thepurpose of its use. For example, when the electromagnetic wave radiationis more important than the change of period, the amplitude of the spreadspectrum modulation need to be made larger and when the change of periodis required to be small, the amplitude of the spread spectrum modulationneeds to be made smaller. Therefore, it is made possible to arbitrarilyset the output code which the control circuit outputs in order toincrease the flexibility of the SSCG circuit chip and deal with variouspurposes.

Even though it is made possible to arbitrarily set an output code to beapplied to an IDAC, the configuration of the IDAC itself is fixed in achip and the range in which the input current Iref can be changed andthe minimum step (resolution) for change are fixed. FIG. 30A to FIG. 30Cshow the change of an output code when the amplitude is changed, and inaccordance with the change of the output code, the current changes, andthe differential current which changes in such a way as shownschematically, can be obtained. As shown in FIG. 30A, when the amplitudeis large, the amplitude is large compared with the minimum step and thecurrent changes in a relatively smooth manner. In contrast to this, whenthe amplitude is halved, the change becomes less smooth as shown in FIG.30B than the case shown in FIG. 30A. If the amplitude is further halved,that is, when the amplitude is ¼ the original amplitude, the change ofthe differential current signal becomes still less smooth as shown inFIG. 30C. As the change of the differential current signal becomes lesssmooth, the high-frequency component of the current to be applied to theICO increases and the operation of PLL is adversely affected.

In order to obtain a differential current signal which changes in asufficiently smooth way even when the amplitude is made smaller, it isnecessary to increase the number of bits of an output code by increasingthe number of transistors. For example, a nine-bit output code isnecessary for the ability to adjust an amplitude with five bits, thatis, the ability to adjust the amplitude in the range from 100% to 3%,and for the resolution of four bits for the minimum amplitude, that is,the resolution adjustable in 15 steps. In the circuit configurationshown in FIG. 18, when n=9, it is necessary to make the size of thetransistor with the maximum size 2⁸=256 times the size of that with theminimum size, and to make the chip area 2⁹=512 times the area of thetransistor with the minimum size. Therefore, the size of Tr3 n and Tr4 nis 256 times the size of Tr30 and Tr40. As the size of the transistorwith the minimum size is determined by the manufacturing process, aproblem arises that the size of the transistor with the maximum sizebecomes very large and the area required for the size also becomeslarge.

The transistor train with the circuit size ratio shown in FIG. 18 isrealized by forming a plurality of transistors with minimum size inparallel and changing the number of transistors with minimum size inpowers of two, that is, the minimum size transistor is formed by one ofthe transistors with minimum size, the second smallest size transistoris formed by two of the transistors with minimum size connected inparallel, the third smallest size transistor is formed by four of thetransistors with minimum size connected in parallel, and so on. In thiscase, if n=9, the maximum sized transistor is formed by connecting inparallel 256 of the transistors with minimum size. Therefore, in orderto realize the set of Tr30 and Tr40 from the set of Tr3 and Tr4 n, 512sets of Tr30 and Tr40 are necessary.

Either way, the size of transistor increases at a rate of powers of twowhen the number of bits of an output code is increased, therefore, aproblem arises that the circuit scale and the cost increase.

It is possible for the spread spectrum clock generation (SSCG) circuitto be described below according to the third aspect of the presentinvention to ensure a wide amplitude adjustable range and a sufficientresolution even for the minimum amplitude without increasing the circuitscale so much.

FIG. 31A and FIG. 31B show the configuration based on the principle ofthe SSCG circuit according to the third aspect of the present invention.

As shown in FIG. 31A, the spread spectrum clock generation circuit ofthe present invention is provided with a spread spectrum modulationcircuit 71 and an amplifying circuit 72, and after going through thespread spectrum modulation and the amplitude adjustment separately, thedifferential current signal is added to the original differentialcurrent signal. In concrete terms, the spread spectrum modulationcircuit 71 and the amplifying circuit 72 are cascaded, and after thedifferential current signal output from the voltage-current (V-I)conversion circuit 42 is modulated in the spread spectrum modulationcircuit 71, the spread spectrum modulation signal is amplified and theamplitude is adjusted in the amplifying circuit 72, then the signal theamplitude of which is adjusted is added to the original differentialcurrent signal and applied to the ICO 44.

As shown in FIG. 31A and FIG. 31B, the order of the spread spectrummodulation circuit 71 and the amplifying circuit 72 can be reversed.

FIG. 32A and FIG. 32B are diagrams illustrating the principle of thethird aspect of the present invention: FIG. 32A shows the modulatedcurrent signal after a pattern modulation with n-bit is carried out on adifferential current signal with amplitude A in the spread spectrummodulation circuit 71; and FIG. 32B shows the signal shown in FIG. 32Athe amplitude of which has been amplified (attenuated) by a factor ofk/m. Even if the amplitude is amplified by a factor of k/m, theresolution (number of steps) does not change.

In the SSCG circuit of the third aspect of the present invention, as thepattern modulation and the amplitude adjustment are carried outindependently, a modulated current with a constant resolutionindependent of the amplitude adjustment is output. As described above,in order to realize the 5-bit amplitude adjustment and the 4-bitresolution for the minimum amplitude in the conventional configurationin FIG. 3, an area 2⁹=512 times the size of the set of the minimum sizedtransistors Tr30 and Tr40 is required to obtain Tr3 n from Tr30, and Tr4n from Tr40 when n=9. In contrast to this, in the spread spectrum clockgeneration circuit of the present invention, only an area 2⁵+2⁴=48 timesthe size is required, therefore, the circuit scale can be reduced.

If the SSCG circuit in the seventh embodiment shown in FIG. 27 iscompared with the SSCG circuit in the third aspect shown in FIG. 31A, itwill be found that both have the same configuration. In other words, theSSCG circuit in the seventh embodiment realizes the third aspect.

As described above, the IDAC also operates as an amplifying circuit,therefore, the spread spectrum modulation circuit 71 and the amplifyingcircuit 72 can be realized by the use of the current digital-to-analogconversion circuit (IDAC) shown in FIG. 18.

FIG. 33 is a diagram showing the configuration of the spread spectrumclock generation (SSCG) circuit in the eighth embodiment of the presentinvention. As shown schematically, the SSCG circuit in the eighthembodiment has a configuration similar to that of the SSCG circuit inthe seventh embodiment, a pattern IDAC 73 has a configuration similar tothat of the first IDAC 63 shown in FIG. 28, and a level IDAC 74 has aconfiguration similar to that of the second IDAC 64 shown in FIG. 29.

As shown in FIG. 33, in the SSCG circuit in the eighth embodiment, thedifferential current signal, which the V-I converter 42 in the currentoscillation circuit 41 outputs, is applied to the ICO 44 and at the sametime input to the pattern IDAC 73. The pattern IDAC 73 carries out thespread spectrum modulation on the differential current signal inaccordance with the output code output from a pattern control circuit 75and generates a spread spectrum modulation signal. The level IDAC 74amplifies (attenuates) the spread spectrum modulation signal inaccordance with the output code output from a level control circuit 76and adjusts the amplitude.

The output code output from the level control circuit 76 is adjusted bythe outside in accordance with the purpose of use and has a constantvalue.

The pattern control circuit 75 outputs a spread spectrum modulationcode.

FIG. 34A and FIG. 34B are diagrams showing the configuration andoperation of the pattern control circuit 33 realized by the use of adigital logic circuit. As shown in FIG. 34A, the pattern control circuit75 comprises an up/down counter 77 for counting a clock and a dividingcounter 78 for controlling the up/down counter 77. The up/down counter77 outputs a count value in an n-bit binary code. As shown in FIG. 34B,the dividing counter 78 counts a clock and when the count value reachesa predetermined value, the up count operation and the down countoperation of the up/down counter are switched. In this manner, an outputcode which changes in such a way as shown in FIG. 34B is obtained. Here,it is desirable for the count value to change between the maximum valueand the minimum value specified by the number of bits.

FIG. 35 is a diagram showing the configuration of the SSCG circuit inthe ninth embodiment of the present invention. Although the patterncontrol circuit 75 and the level control circuit 76 are realized by theuse of a logic circuit in the eighth embodiment, these are realized bythe use of a computer system such as a microcomputer and a DSP in theninth embodiment. Other parts are the same as those in the eighthembodiment.

As described above, according to the eighth and ninth embodiments, aspread spectrum clock generation circuit, which ensures a wide amplitudeadjustable range and a sufficient resolution for the minimum amplitude,can be realized with a small circuit scale and a spread spectrum clockgeneration circuit having a high flexibility can be obtained at a lowcost.

In the SSCG circuit using the IDAC described above, it is general tochange a current to be input to the ICO 44 so as to have a triangularwave shape as shown in FIG. 36A. In the case of an IDAC with 2-bitconfiguration, a current is changed in only four steps as shown in FIG.36B. In the case of an IDAC with 3-bit configuration, a current ischanged in only eight steps as shown in FIG. 36C. As described above, ifthe number of bits of an IDAC is small, the step width with which acurrent changes becomes wider as shown in FIG. 36B and FIG. 36C, thehigh frequency component in the current to be applied to the ICOincreases, and a problem arises that the PLL operation is adverselyaffected and at the same time the electromagnetic radiation is notreduced sufficiently.

In order to make smooth the change of the current to be input to the ICOand reduce the electromagnetic radiation sufficiently in the IDAC withthis configuration, it is necessary to increase the number of bits ofthe IDAC. For example, the IDAC has a 5-bit configuration, in which acurrent is changed into 32 steps, but this is still insufficient and itis necessary to further increase the number of bits of the IDAC 17.However, if the number of bits of the IDAC is increased, the size of theIDAC and the circuit scale of the control circuit become largeraccordingly, and a problem arises that the cost is raised.

In the spread spectrum clock generation (SSCG) circuit in the fourthaspect of the present invention, it is possible to further reduce theelectromagnetic radiation with a simple configuration.

FIG. 37 is a diagram showing the basic configuration of the SSCG circuitin the fourth aspect of the present invention.

As shown in FIG. 37, in the SSCG circuit in the fourth aspect of thepresent invention, a current injection circuit 81 is connected to theconnection node of a resistor R and a capacitor C making up theloop-filter 14, and the charging and discharging are carried out in sucha way that the voltage of the capacitor C changes with a voltageamplitude smaller than the voltage of the capacitor in a spread spectrumperiod longer than the generated clock period.

FIG. 38 is a diagram showing the basic configuration of the currentinjection circuit 81. As shown in FIG. 38, the current injection circuitcomprises two switches 84 and 85 connected in series between a constantcurrent source 82 on the high potential power source side and a constantcurrent source 83 on the low potential power source side, and controlsthe switches 84 and 85 by the use of a charge signal and a dischargesignal, which are in a complementary relationship. Charging is carriedout when the switch 84 is in the state of connection and the switch 85is in the state of cutoff, and discharging is carried out when theswitch 84 is in the state of cutoff and the switch 85 is in the state ofconnection.

According to the fourth aspect of the present invention, when the inputvoltage (differential voltage signal) of the VCO or the currentoscillation circuit is changed, the control voltage of the VCO or thecurrent oscillation circuit also changes, therefore, it is possible torealize a clock generation circuit which can reduce the electromagneticradiation by effecting the oscillation frequency transition of the clockgenerated by the VCO or the current oscillation circuit. In the presentinvention, as the voltage of a capacitor is changed by carrying outcharging and discharging of the capacitor making up the loop-filter, thevoltage of the capacitor increases or decreases at a constant rate ifthe current used for charging and discharging is constant, therefore,the change is smooth as shown in FIG. 36A. Therefore, the currentinjection circuit 81 requires only the use of a small-scalecurrent-source circuit and a simple current source control circuit forswitching between the charging period and the discharging period, and itis possible to reduce a glitch caused by the step-wise change even ifthe circuit scale of the whole SSCG circuit is made smaller. If thecurrent used for charging and discharging is constant, it is possible tochange the period and amplitude of the voltage change of the capacitorby controlling the time for charging and discharging. As described sofar, the current source used as the current injection circuit 81 can beeasily controlled in a digital manner and it is possible to effect thefrequency transition more exactly and more precisely than when thespread spectrum process is carried out using a general D/A converter asa VCO.

FIG. 39 is a diagram showing the configuration of the SSCG circuit inthe tenth embodiment of the present invention. As obvious from thecomparison with the SSCG circuit in FIG. 13, the SSCG circuits in thetenth embodiment has a configuration modified from that of the SSCGcircuit in the third embodiment by eliminating the IDAC 17 and thecontrol circuit 19, and by connecting a current injection circuitconsisting of a current source control circuit 86, a reference currentsource 87 and a current source 88 to the connection node of the resistorR and the capacitor C making up the loop-filter 14. Therefore, thedescription about the configuration of the frequency phase comparator12, the charge pump 13, the V-I conversion circuit 16, the ICO circuit18, and so on, is not given here.

FIG. 40 is a diagram showing the circuit configuration of the referencecurrent source circuit 87, FIG. 41 is a diagram showing the circuitconfiguration of the current source control circuit 86, and FIG. 42 is adiagram showing the circuit configuration of the current source circuit88.

The reference current source circuit 87 is a widely known current mirrorcircuit and a reference current whose amount of current is constant isoutput. The current source control circuit 86 comprises a 1/K dividingcircuit 89 and generates a clock signal with a duty ratio of 50% in thespread spectrum modulation period by dividing the reference clock CLK bya factor of 1/K. The generated clock signal is output as a charge signaland at the same time inverted in an inverter 90 and output as adischarge signal. Therefore, the charge signal and the discharge signalare complementary signals.

In the current source circuit 88, the current mirror circuit is composedof transistors Tr71 to Tr75, and the transistor Tr74 serves as aconstant current source which charges the reference current output fromthe reference current source 87, and the transistor Tr75 serves as aconstant current source which discharges the reference current. Betweenthe transistors Tr74 and Tr75, transistors Tr76 and Tr77 are connectedin series and a charge signal is applied to the gate of the transistorTr76 via an inverter and a discharge signal is applied to the gate ofthe transistor Tr77. When the charge signal is at “high (H)” and thedischarge signal is at “low (L)”, the transistor Tr76 is set to the ONstate, the transistor Tr77 is set to the OFF state, and a current inaccordance with the reference current is output via the transistors Tr74and Tr76 so as to charge the capacitor C. When the charge signal is at“L” and the discharge signal is at “H”, the transistor Tr76 is set tothe OFF state, the transistor Tr77 is set to the ON state, and a currentin accordance with the reference current is drained in via thetransistors Tr76 and Tr75 so as to discharge the capacitor C.

FIG. 43A to FIG. 43D are diagrams showing the change in the currentwhich flows through the current source 88 in accordance with the chargesignal and the discharge signal and the change of the voltage (VCOcontrol voltage) of the connection node of the resistor R and thecapacitor C making up the loop-filter 14. As shown schematically, whenthe charge signal is at “H” and the discharge signal is at “L”, thecurrent source 88 outputs a constant current and in accordance withthis, the VCO control voltage increases, and when the charge signalswitches to “L” and the discharge signal switches to “H”, the currentsource 88 drains a constant current and, in accordance with this, thecontrol voltage of the current oscillation circuit 41 decreases,changing into a triangular wave shape. In accordance with this, thefrequency of the clock CK, which the current oscillating circuit 41generates, changes.

FIG. 44 is a diagram showing the configuration of the SSCG circuit inthe eleventh embodiment of the present invention. As shownschematically, the SSCG circuit in the eleventh embodiment differs fromthe SSCG circuit in that the reference current source 87 is removed andthe output of the V-I conversion circuit 42 is input as the referencecurrent of the current source 88.

In the SSCG circuit in the tenth embodiment, the reference circuit isconstant and regardless of the VCO control voltage, the current to besupplied to or to be drained from the capacitor changes in apredetermined way and the spread spectrum voltage is constant.Therefore, the ratio of the spread spectrum voltage to the VCO controlvoltage differs depending on the VCO control voltage. As a result, if itis assumed that the oscillating frequency is in proportion to the VCOcontrol voltage, the ratio of the frequency which changes according tothe spread spectrum modulation is different between a low frequency anda high frequency. In contrast to this, in the SSCG circuit in the secondembodiment, as the reference current changes in accordance with the VCOcontrol voltage, the ratio of frequency which changes according to thespread spectrum modulation is the same for the low frequency and thehigh frequency. Because of this, in the SSCG circuit in the eleventhembodiment, it is possible to carry out the spread spectrum modulationat the same ratio for each oscillating frequency.

Moreover, in the SSCG circuit in the tenth and eleventh embodiments, thePLL circuit is formed in such a way that the clock CK generated in thecurrent oscillation circuit 41 is fed back. Therefore, even if thecharacteristic of the ICO 44, as a single unit, or the currentoscillation circuit 41 changes because of the variations inmanufacturing process, changes in temperature or changes in currentsource voltage, a clock CK in accordance with the frequency of thereference clock CLK is finally generated. In the tenth embodiment,however, as the feedback is not carried out in the circuit portion wherethe spread spectrum modulation process is carried out, the spreadspectrum modulation process is affected by such variations. In contrastto this, in the second embodiment, as the output current of the V-Iconverter 42 is reflected in the current source output current byfeeding back the output current as the reference current of the currentsource 88, that is, as the feedback is also carried out for the spreadspectrum modulation process, the control voltage of the currentoscillation circuit 41 is not affected by the variations and a clock CKhaving a desired spread width is output.

FIG. 45 is a diagram showing the configuration of the SSCG circuit inthe twelfth embodiment of the present invention. As shown schematically,the SSCG circuit in the twelfth embodiment differs from the SSCG circuitin the eleventh embodiment in that, after being filtered by a low-passfilter (LPF) 91 in order to remove the high frequency component, theoutput of the V-I conversion circuit 42 is input as the referencecurrent of the current source 88. Because of this, unlike the eleventhembodiment, it is possible to remove the spread spectrum component fromthe output of the V-I conversion circuit 42 and carry out the spreadspectrum modulation at a constant spread rate all the time.

FIG. 46 is a diagram showing the configuration of the SSCG circuit inthe thirteenth embodiment of the present invention. As shownschematically, in the SSCG circuit in the thirteenth embodiment, afterbranching from and being filtered by an LPF 92, the VCO control voltageto be input to a VCO 17′ is converted into a current signal in a V-Iconversion circuit 93 and fed back as the reference current of thecurrent source 88. In the thirteenth embodiment, as a voltage signal isfiltered, the LPF 92 can be realized by a simple circuit by the use ofcapacitors and resistors, it is possible to reduce the circuit size andat the same time obtain the same effects as those of the twelfthembodiment.

FIG. 47 is a diagram showing the configuration of the SSCG circuit inthe fourteenth embodiment of the present invention. As shownschematically, the SSCG circuit in the fourteenth embodiment differsfrom that in the tenth embodiment in that an IDAC control circuit 94 andan IDAC circuit 96 are provided instead of the current source controlcircuit 86 and the current source 88.

FIG. 48 is a diagram showing the configuration of the IDAC circuit 96.The IDAC circuit 96 used in the fourteenth embodiment is a push-pulltype, which not only outputs a current but also drains (pulls out) acurrent. The detailed description is not given here.

FIG. 49A to FIG. 49C are diagrams showing the change of the voltage ofthe capacitor C of the loop-filter versus the change of control data DU0to DU2 and DD0 to DD2 of the IDAC circuit 96 shown in FIG. 48: FIG. 49Ashows the case of one-bit drive, FIG. 49B shows the case of two-bitdrive, and FIG. 49C shows the case of three-bit drive.

As shown in FIG. 49A, in the case of one-bit drive, DU0 changes in sucha way as shown schematically, and DU1 and DU2 maintain the “H” state.DD0 and DU0 are identical signals and DD1 and DD2 maintain the “L”state. In this manner, only Tr87 and Tr90 shown in FIG. 48 repeat the ONand OFF states, therefore, an small amount of current is supplied to ordrained from the capacitor C from or by the IDAC 96, and the voltage ofthe capacitor C changes in a triangular wave form with a small-sizedamplitude.

As shown in FIG. 49B, in the case of a two-bit drive, DU0 and DU1 changein such a way as shown schematically, and DU2 maintains the “H” state.DD0 and DD1 are signals identical to DU0 and DU1, respectively, and DD2maintains the “L” state. In this manner, Tr87, Tr88, Tr90 and Tr91 shownin FIG. 48 repeat the ON and OFF states, therefore, a medium amount ofcurrent is supplied to or drained from the capacitor C from or by theIDAC 96 and the voltage of the capacitor C changes in a triangular waveform with a middle-sized amplitude.

As shown in FIG. 49C, in the case of a three-bit drive, DU0 to DU2change in such a way as shown schematically, and DD0 to DD2 are signalsidentical to DU0 to DU2, respectively. In this manner, Tr87 to Tr89 andTr90 and Tr92 shown in FIG. 48 repeat the ON and OFF states, therefore,a large amount of current is supplied to or drained from the capacitor Cfrom or by the IDAC 96 and the voltage of the capacitor C changes in atriangular wave form with a large-sized amplitude.

As described above, it is possible to change the amount of current forcharging and discharging the capacitor C in the SSCG circuit in thefourteenth embodiment.

The IDAC control circuit 94 outputs the control data DU0 to DU2 and DD0to DD2 as shown in FIG. 49A to FIG. 49C. Although the IDAC controlcircuit 94 can be realized by the use of a dedicated logic circuit, itis also possible to realize by the use of a micro computer or DSP.Moreover, a reference current source 95 has a configuration similar tothat of the circuit shown in FIG. 40.

It can be said that the current source 88 in the tenth embodimentrepresents a case where the IDAC in the fourteenth embodiment is changedinto a one-bit configuration.

FIG. 50 is a diagram showing the configuration of the SSCG circuit inthe fifteenth embodiment of the present invention. The SSCG circuit inthe fifteenth embodiment has a configuration modified from that of theSSCG circuit in the eleventh embodiment by replacing the current sourcecontrol circuit 86 and the current source 88 with the IDAC controlcircuit 94 and the IDAC circuit 96 in the fourteenth embodiment.Therefore, this SSCG circuit has the characteristic of the fourteenthembodiment in addition to that of the eleventh embodiment.

FIG. 51 is a diagram showing the configuration of the SSCG circuit inthe sixteenth embodiment of the present invention. The SSCG circuit inthe sixteenth embodiment has a configuration modified from that of theSSCG circuit in the twelfth embodiment by replacing the current sourcecontrol circuit 86 and the current source 88 with the IDAC controlcircuit 94 and the IDAC circuit 96 in the fourteenth embodiment.Therefore, this SSCG circuit has the characteristic of the fourteenthembodiment in addition to that of the twelfth embodiment.

FIG. 52 is a diagram showing the configuration of the SSCG circuit inthe seventeenth embodiment of the present invention. The SSCG circuit inthe seventeenth embodiment has a configuration modified from that of theSSCG circuit in the thirteenth embodiment by replacing the currentsource control circuit 86 and the current source 88 with the IDACcontrol circuit 94 and the IDAC circuit 96 in the fourteenth embodiment.Therefore, this SSCG circuit has the characteristic of the fourteenthembodiment in addition to that of the thirteenth embodiment.

FIG. 53 is a diagram showing the configuration of the semiconductordevice having a jitter generation circuit in the eighteenth embodimentof the present invention. As shown in FIG. 53, a semiconductor device101 in the eighteenth embodiment comprises a clock generation circuit102, a jitter generation circuit 102, a selection signal generationcircuit 104 and an internal circuit 105. The clock generation circuit102 generates and outputs an input clock signal CLKIN as a referenceinput signal based on the oscillation signal of a crystal oscillator.Here, the input clock signal CLKIN output from the clock generationcircuit 102 changes in a sinusoidal wave form in a constant period T, asshown in FIG. 54.

The jitter generation circuit 103 is provided between the clockgeneration circuit 102 and the internal circuit 105, and the jittergeneration circuit 103 outputs an output clock signal CLKOUT, which isthe input clock signal CLIKIN from the clock generation circuit 102 towhich a jitter (a jitter in the time axis direction) is added by thejitter generation circuit 103, to the internal circuit 105.

The internal circuit 105 comprises a widely known CPU 105 a and aperipheral circuit 105 b (for example, RAM, ROM, input/output circuit)and operates based on the output clock signal CLKOUT from the jittergeneration circuit 103.

The selection signal generation circuit 104 comprises a flip-flopcircuit, which is not shown, and generates a selection signal VTSELbased on the input clock signal CLKIN from the clock generation circuit102 and outputs it to the jitter generation circuit 103. As shown inFIG. 54, the voltage level of the selection signal VTSEL changes to theH level or the L level with the timing in accordance with the period Tof the input clock signal CLKIN (in concrete terms, the timing withwhich the level of the input clock signal CLKIN reaches the maximumvalue).

The jitter generation circuit 103 in the eighteenth embodiment comprisesa normal inverter circuit 106 not having the hysteresis characteristic,a hysteresis inverter circuit 107 having the hysteresis characteristic,and a switch circuit 108. The jitter generation circuit 103 is providedwith a first input terminal 103 a which inputs the input clock signalCLKIN from the clock generation circuit 102, a second input terminal 103a which inputs the selection signal VTSEL from the selection signalgeneration circuit 104, and an output terminal 103 c which outputs theoutput clock signal CLKOUT.

In the jitter generation circuit 103, the inverter circuit 106 and thehysteresis inverter circuit 107 are connected to the first inputterminal 103 a and the clock signal CLKIN is input to each invertercircuit 106 and 107. In addition, the inverter circuit 106 and thehysteresis inverter circuit 107 are connected to the output terminal 103c via the switch circuit 108.

As described above, the spread spectrum modulation process of currentcontrol type is carried out in the tenth to seventeenth embodiments and,therefore, the following effects can be obtained.

(1) The electromagnetic wave radiation can be reduced by effectivelyspreading the spectrum of the oscillating frequency,

(2) the degree of the spectrum of the oscillating frequency can be setfreely,

(3) the oscillating frequency transition can be carried out precisely,and

(4) the affect of the variations in process, temperature, power supplyvoltage, and so on, can be reduced.

Moreover, in comparison with the case where the IDAC shown in FIG. 18 isused, the effect that

(5) a more precise spread spectrum modulation process can be carried outwith a small scale circuit configuration can be obtained.

The threshold voltage of the hysteresis inverter circuit 107 is largerthan the threshold voltage of the inverter circuit 106 when the outputis switched from the H level (first level) to the L level (secondlevel), and smaller than the threshold voltage of the inverter circuit106 when the output is switched from the L level to the H level.

The output of the inverter circuit 106 changes from the H level to the Llevel when the input clock signal CLKIN exceeds the voltage value VH1 inFIG. 54, and changes from the L level to the H level when the inputclock signal CLKIN falls below the voltage value VL1. On the other hand,the output of the hysteresis inverter circuit 107 changes from the Hlevel to the L level when the input clock signal CLKIN exceeds thevoltage value VH2 and changes from the L level to the H level when theinput clock signal CLKIN falls below the voltage value VL2. Therelationship of each voltage value is VH2>VH1>VL1>VL2.

The switch circuit 108 connects one of the inverter circuit 106 and thehysteresis inverter circuit 107 to the output terminal 103 c inaccordance with the voltage level of the selection signal VTSEL. Inconcrete terms, the switch circuit 108 connects the inverter circuit 106and the output terminal 103 c when the selection signal VTSEL is at theH level and connects the hysteresis inverter circuit 107 and the outputterminal 103 c when the selection signal VTSEL is at the L level.

Therefore, in the jitter generation circuit 103, as shown in FIG. 54,the output clock signal CLKOUT changes to the H level or the L level inaccordance with the input clock signal CLKIN. To be exact, before timet1, the selection signal VTSEL is at the H level and the invertercircuit 106 is connected to the output terminal 103 c via the switchcircuit 108. Therefore, the output clock signal CLKOUT changes from theH level to the L level at time t1 when the voltage level of the inputclock signal CLKIN exceeds the voltage value VH1.

Then, the selection signal VTSEL changes to the L level and the outputclock signal CLKOUT changes from the L level to the H level at time t2when the voltage level of the input clock signal CLKIN falls below thevoltage value VL2, because the hysteresis inverter circuit 107 isconnected to the output terminal 103 c via the switch circuit 108. At asubsequent time 3 when the voltage level of the input clock signal CLKINexceeds the voltage value VH2, the output clock signal CLKOUT changesfrom the H level to the L level.

Because the selection signal VTSEL changes to the H level between thetime t3 and a time t4 and the inverter circuit 106 is connected to theoutput terminal 103 c via the switch circuit 108, the output clocksignal CLKOUT changes from the L level to the H level at the time t4when the voltage level of the input clock signal CLKIN falls below thevoltage value VL1. Then, at a time t5 also, as at the time t1, when thevoltage level of the input clock signal CLKIN exceeds the voltage valueVH1, the output clock signal CLKOUT changes from the H level to the Llevel. Moreover, at a time t6, when the voltage level of the input clocksignal CLKIN falls below the voltage value VL2, the output clock signalCLKOUT changes from the L level to the H level.

In other words, the output signal CLKOUT in the jitter generationcircuit 103 changes to the L level during a period of time T1 betweenthe times t1 and t2, and changes to the H level during a period of timeT2 between the times t2 and t3. Similarly, it changes to the L levelduring a period of time T3 between the times t3 and t4, changes to the Hlevel during a period of time T4 between the times t4 and t5, andchanges to the L level during a period of time T5 between the times t5and t6. The period of time T1 is longer than the period of time T2 andthe period of time T2 is longer than the period of time T3 (T1>T2>T3).The period of time T4 is equal to the period of time T2 and the periodof time T5 is equal to the period of time T1.

In this manner, in the jitter generation circuit 103 in the eighteenthembodiment, the connection positions of the switch circuit 108 areswitched based on the selection signal VTSEL and one of the invertercircuits 106 and 107, each having a different threshold voltage fromeach other, is connected to the output terminal 103 c. Because of this,the threshold voltage of the jitter generation circuit 103 is changed,and the reversing timing of the output level changes with respect to theconstant-interval timing in accordance with a period T of the inputclock signal CLKIN. As a result, the output clock signal CLKOUT to whicha jitter is added is output from the jitter generation circuit 103.

As described above, the circuit in the eighteenth embodiment has thefollowing effects.

(1) The jitter generation circuit 103 is composed of the invertercircuit 106, the hysteresis inverter circuit 107 and the switch circuit108. In this case, it is possible to add a jitter with a simpler circuitconfiguration than that-of the prior art. Moreover, when the frequencyof the input clock signal CLKIN is changed in accordance with thepurpose of use of the semiconductor device 101, the jitter of the outputclock signal CLKOUT changes according to the frequency and the ratio ofthe jitter to the input clock signal CLKIN can be maintained almostconstant. Therefore, it is possible to effectively reduce the radiationnoise of the semiconductor device 101.

(2) Because the jitter generation circuit 103 can be composed of asimple circuit, the manufacturing cost of the semiconductor device 101can be reduced.

(3) The selection signal circuit 104 generates the selection signalVTSEL based on the input clock signal CLKIN from the clock generationcircuit 102 and the connection positions of the switch circuit 108 areswitched based on the selection signal VTSEL. In this configuration,therefore, it is possible to precisely generate the selection signalVTSEL in accordance with the input clock signal CLKIN. Moreover, as theselection signal generation circuit 104 has a relatively simple circuitconfiguration using a flip-flop circuit, it is preferable for practicaluse.

Next, the nineteenth embodiment of the present invention is describedbelow. The semiconductor device in the nineteenth embodiment comprises ajitter generation circuit 111 shown in FIG. 55 instead of the jittergeneration circuit 103 in the eighteenth embodiment. As the clockgeneration circuit 102, the selection signal generation circuit 104 andthe internal circuit 105 making up the semiconductor device are the sameas those in the eighteenth embodiment, a detailed description is notgiven here.

As shown in FIG. 55, the jitter generation circuit 111 is provided witha first input terminal 111 a which inputs the input clock signal CLKINfrom the clock generation circuit 102, a second input terminal 111 bwhich inputs the selection signal VTSEL from the selection signalgeneration circuit, and an output terminal 111 c which outputs theoutput clock signal CLKOUT.

The jitter generation circuit 111 is composed of P-channel MOStransistors TP1 to TP4 and N-channel MOS transistors TN1 to TN4. In thejitter generation circuit 111, the P-channel MOS transistors TP1 andTP2, and the N-channel MOS transistors TN1 and TN2 are connected inseries between a power source Vcc and a ground GND. Each gate terminalof these transistors TP1, TP2, TN1 and TN2 is connected to the firstinput terminal 111 a and the input clock signal CLKIN is input to eachgate terminal. The connection point of the transistor TP1 and thetransistor TP2 is connected to the ground GND via the P-channel MOStransistor TP3 and the N-channel MOS transistor TN4. On the other hand,the connection point of the transistor TN1 and the transistor TN2 isconnected to the power source Vcc via the N-channel MOS transistor TN3and the P-channel MOS transistor TP4.

The gate terminal of the transistor TP3 is connected to the gateterminal of the transistor TN3 and the connection point thereof isconnected to the connection point of the transistor TP2 and thetransistor TN1, and to the output terminal 111 c. The gate terminals ofthe transistor TN4 and the transistor TP4 are connected to the secondinput terminal 111 b and to these gate terminals, the selection signalVTSEL generated in the selection signal generation circuit 104 is input.

In the jitter generation circuit 111, the circuit excluding thetransistors TP3, TP4, TN3 and TN4, that is, the circuit consisting ofthe transistors TP1, TP2, TN1 and TN2 functions as a normal invertercircuit. In the jitter generation circuit 111, when the transistor TN4is eliminated, the transistor TP3 is connected to the ground GND, thetransistor TP4 is eliminated, and the transistor TN3 is connected to thepower supply Vcc, the circuit functions as a hysteresis invertercircuit. The transistor TP3 and the transistor TN3 serve as a transistorwhich provides the hysteresis characteristic to the inverter circuitconsisting of the transistors TP1, TP2, TN1 and TN2. On the other hand,the transistor TN4 and the transistor TP4 serves as a switch which cutsoff the transistor TP3 and the transistor TN3 from the inverter circuit.

In the jitter generation circuit 111, when the selection signal VTSEL isat the H level and the transistor TN4 is turned on, the thresholdvoltage at which the output clock signal CLKOUT changes from the L levelto the H level becomes lower. On the other hand, when the selectionsignal VTSEL is at the L level and the transistor TP4 is turned on, thethreshold voltage at which the output clock signal CLKOUT changes fromthe H level to the L level becomes higher.

To be exact, when the selection signal VTSEL at the H level is input tothe jitter generation circuit 111, the transistor TN4 is turned on andthe transistor TP4 is turned off. In this state, when the voltage levelof the input clock signal CLKIN is high and the output terminal 111 c(output clock signal CLKOUT) is at the L level, the transistor TP3 isturned on. Therefore, the threshold voltage at which the output terminal111 c changes from the L level to the H level becomes lower than thethreshold voltage of the inverter circuit consisting of the transistorsTP1, TP2, TN1 and TN2. On the other hand, when the voltage level of theinput clock signal CLKIN is low and the output terminal 111 c is at theH level, the transistor TP3 is turned off. At this time, as thetransistor TP4 is in the OFF state, the power supply Vcc is not suppliedto the transistor TN3, that is, the transistor TN3 is in the state ofbeing cut off from the inverter circuit. Therefore, the thresholdvoltage at which the output terminal 111 c changes from the H level tothe L level is equal to the threshold voltage of the inverter circuitconsisting of the transistors TP1, TP2, TN1 and TN2.

On the other hand, when the selection signal VTSEL at the L level isinput to the jitter generation circuit 111, the transistor TN4 is turnedoff and the transistor TP4 is turned on. In this state, the thresholdvoltage at which the output terminal 111 c changes from the H level tothe L level is higher than the threshold voltage of the inverter circuitconsisting of the transistors TP1, TP2, TN1 and TN2. The thresholdvoltage at which the output terminal 111 c changes from the L level tothe H level is equal to the threshold voltage of the inverter circuitconsisting of the transistors TP1, TP2, TN1 and TN2.

Therefore, in the jitter generation circuit 111, when the selectionsignal VTSEL is at the H level and the input clock signal CLKIN exceedsthe voltage value VH1 (times t11 and t15), the output clock signalCLKOUT changes from the H level to the L level, as shown in FIG. 56.When the selection signal VTSEL is at the H level and the input clocksignal CLKIN falls below the voltage value VL2 (time t14), the outputclock signal CLKOUT changes from the L level to the H level.

On the other hand, when the selection signal VTSEL is at the L level andthe input clock signal CLKIN. exceeds the voltage value VH2 (time t13),the output clock signal CLKOUT changes from the H level to the L level.When the selection signal VTSEL is at the L level and the input clocksignal CLKIN falls below the voltage value VL1 (times t12 and t16), theoutput clock signal CLKOUT changes from the L level to the H level.

In other words, the output clock signal CLKOUT in the jitter generationcircuit 111 is at the L level during a period of time T11 between thetimes t11 and t12 and at the H level during a period of time T12 betweenthe times t12 and t13. Similarly, the output clock signal CLKOUT is atthe L level during a period of time T13 between the times t13 and t14,at the H level during a period of time T14 between the times t14 andt15, and at the L level during a period of time T15 between the timest15 and t16. The period of time T11 is equal to the period of time T13and the period of time T15, and shorter than the period of time T12(T11=T13 =T15<T12). The period of time T14 is shorter than the period oftime T11 (T11>T14).

In this manner, in the jitter generation circuit 111 in the presentinvention also, the threshold voltage is changed in accordance with theselection signal VTSEL, therefore, the reversing timing of the outputlevel is changed with respect to the constant-interval timing inaccordance with the period T of the input clock signal CLKIN. As aresult, the output clock signal CLKOUT to which a jitter is added isoutput.

As described above, the circuit in the nineteenth embodiment has thefollowing effects.

(1) The jitter generation circuit 111 is composed of the MOS transistorsTP1 to TP4, and TN1 to TN4. In this case, it is possible to add a jitterwith a simpler circuit configuration that that of the prior art.Moreover, when the frequency of the input clock signal CLKIN is changed,the jitter of the output clock signal CLKOUT changes according to thefrequency, therefore, it is possible to effectively reduce the radiationnoise of the semiconductor device 101.

The eighteenth and nineteenth embodiments can be modified as below.Instead of the jitter generation circuits 103 and 111, a jittergeneration circuit 121 shown in FIG. 57 and a jitter generation circuit131 shown in FIG. 58 can be used.

To be exact, the jitter generation circuit 121 shown in FIG. 57comprises a normal NAND circuit 122 not having the hysteresischaracteristic, a NAND circuit 123 having the hysteresis characteristic,and an inverter circuit 124. The jitter generation circuit 121 isprovided with a first input terminal 121 a which inputs the input clocksignal CLKIN, a second input terminal 121 b which inputs a controlsignal CNTL, and an output terminal 121 c which outputs the output clocksignal CLKOUT. The first input terminal 121 is connected to one of theinput terminals of the NAD circuit 122 and the NAND circuit 123, and thesecond input terminal 121 b is connected to the other input terminal ofthe NAND circuit 122 and at the same time connected to the other inputterminal of the NAND circuit 123 via the inverter circuit 124. The NANDcircuit 122 and the NAND circuit 123 are connected to the outputterminal 121 c.

In this jitter generation circuit 121 also, the threshold voltage ischanged in accordance with the voltage level of the control signal CNTL,as each of the embodiments described above, and it is possible to outputthe output clock signal CLKOUT to which a jitter is added.

The jitter generation circuit 131 shown in FIG. 58 comprises a firstinverter circuit 132 consisting of a P-channel MOS transistor TP5 and anN-channel MOS transistor TN5, a second inverter circuit 133 consistingof a P-channel MOS transistor TP6 and an N-channel MOS transistor TN6,and a switch circuit 134. Moreover, the jitter generation circuit 131 isprovided with a first input terminal 131 a which inputs the input clocksignal CLKIN from the clock generation circuit 102, a second inputterminal 131 b which outputs the selection signal VTSEL from theselection signal generation circuit 104, and an output terminal 131 cwhich outputs the output clock signal CLKOUT. The first and secondinverter circuits 132 and 133 are connected to the first input terminal131 a and the circuits 132 and 133 each are connected to the outputterminal 131 c via the switch circuit 134. The switch circuit 134connects one of the first and second inverter circuits 132 and 133 tothe output terminal 131 c in accordance with the voltage level of theselection signal VTSEL.

Moreover, in the jitter generation circuit 131, a threshold voltage Vth1of the first inverter circuit 132 is set higher than a threshold voltageVth2 of the second inverter circuit 133. In concrete terms, in the firstinverter circuit 132, the driving performance of the transistor TP5 isset lower than that of the transistor TN5, and in the second invertercircuit 133, the driving performance of the transistor TP6 is set higherthan that of the transistor TN6. The driving performance of eachtransistor TP5, TP6, TN5 and TN6 is adjusted by changing the gatelength.

In this jitter generation circuit 131 also, the threshold voltage ischanged in accordance with the voltage level of the selection signalVTSEL, as each of the embodiments described above, and it is possible tooutput the output signal CLKOUT to which a jitter is added.

The jitter generation circuit 131 is composed of the two invertercircuits 132 and 133 connected in parallel, each having a differentthreshold voltage, but it is also possible to configure a jittergeneration circuit in which three or more inverter circuits each havinga different threshold voltage is connected in parallel. In thisconfiguration also, a switch circuit is provided between the outputterminal and each inverter circuit and one of the inverter circuits isselectively connected to the output terminal by the switch circuit.

When a clock signal generated in the clock generation circuit 102 has arectangular wave shape, a CR circuit 141 consisting of the capacitor Cand the resistor R is provided between the clock generation circuit 102and each of the jitter generation circuits 103, 111, 121 and 131. Inthis manner, the clock signal CLK having a rectangular wave shapegradually changes its shape into a sinusoidal wave shape as it passesthrough the CR circuit 141. As a result, it is possible to add a properjitter in accordance with the clock signal CLK in the jitter generationcircuits 103, 111, 121 and 131.

The eighteenth and nineteenth embodiments and their modifications areapplicable to a clock signal which operates the internal circuit 105(CPU 105 a and its peripheral circuit 105 b), but they can be applied toother signals such as a synchronous signal used in data communications.

A conventional semiconductor device having a jitter generation circuithas, for example, a configuration as shown in FIG. 60. As shown in FIG.60, in a semiconductor device 151, a clock signal CLK is input to ajitter generation circuit 152 and a jitter is added to the clock signalCLK. Then a clock signal GCLK to which a jitter is added is suppliedfrom the jitter generation circuit 152 to a CPU 153 and its peripheralcircuits (for example, a serial IO 154, a RAM 155, a counter 156, atimer 157 and a parallel IO 158). In such a configuration, the peakvalue of the radiation noise can be reduced.

In the semiconductor device shown in FIG. 60, however, the clock signalGCLK to which a jitter is added is supplied to the entire systemincluding the CPU 153 and the peripheral circuits, therefore, the systemis operated based on the clock signal GCLK containing the same jitter.However, the CPU 153 and the serial IO154 are circuits subject to astrict operation timing and, therefore, it is impossible for the clocksignal GCLK containing a large jitter to operate them. As a result,there has been a problem that a large jitter cannot be added because ofa malfunction of the circuit that can be expected, that is, an optimumjitter which will reduce the radiation noise cannot be added to theclock signal CLK. In the embodiments described below, such a problem canbe solved.

FIG. 61 is a diagram showing the configuration of the semiconductordevice 151 in the twentieth embodiment. The semiconductor device 151comprises the jitter generation circuit 152, the CPU 153, the serialinterface (serial IO) 154, the RAM 155, the counter 156, the timer 157and the parallel interface (parallel IO) 158.

Among the circuits comprised in the semiconductor device 151, the CPU153, the serial IO 154 and the RAM 155 are circuits (first internalcircuit) subject to a strict operation timing, and the counter 156, thetimer 157 and the parallel IO 158 are circuits (second internal circuit)subject to a relatively less strict operation timing.

In the semiconductor device 151, the clock signal CLK from the outsideis input to the jitter generation circuit 152, the CPU 153, the serialIO 154 and the RAM 155. The jitter generation circuit 152 adds a jitterto the clock signal CLK and supplies the clock signal GCLK with thejitter added to the counter 156, the timer 157 and the parallel IO 158.Instead of the jitter generation circuit 152, the jitter generationcircuit in the eighteenth and nineteenth embodiments, the SSCG circuitin the first to seventeenth embodiment and a general jitter generationcircuit can be used.

In the semiconductor 151, the clock signal which is the input signal tothe jitter generation circuit, that is, the precise clock signal CLK towhich no jitter is added, is supplied to the first internal circuit (CPU153, serial IO 154, RAM 155) subject to a strict operation timing,therefore, it is possible to operate each of the circuits 153, 154 and155 at high speed.

The clock signal GCLK to which a jitter is added in the jittergeneration circuit 152 is supplied to the second internal circuit(counter 156, timer 157, parallel IO 158) subject to a relatively lessstrict operation timing. When the entire system is operated by the clocksignal GCLK with a jitter added as in the conventional semiconductordevice shown in FIG. 60, the amount of jitter which can be added to theclock signal CLK is limited to a relatively small range. In contrast tothis, in the semiconductor device in the twentieth embodiment, the clocksignal GCLK to which a jitter is added is supplied only to the circuitssubject to a relatively less strict operation timing, therefore, it ispossible to add a larger amount of jitter to the clock signal GCLK andeffectively reduce the radiation noise.

As described above, in the semiconductor device 151 in the twentiethembodiment, it is possible not only to increase the circuit operationspeed but also to reduce the radiation noise.

FIG. 62 is a diagram showing the configuration of the semiconductordevice 151 in the twenty-first embodiment. In the twenty-firstembodiment, the same symbols are used for those which are the same asthe configuration in the twentieth embodiment. Only the differences fromthe twentieth embodiment is described below.

In other words, the semiconductor device 151 comprises dividing circuits162 and 163, in addition to each circuit (jitter generation circuit 152,CPU 153, serial IO 154, RAM 155, counter 156, timer 157, parallel IO158) in the twentieth embodiment 20.

In the semiconductor device 151, the clock signal CLK from the outsideis input to the dividing circuit 162. The dividing circuit 162 dividesthe clock signal CLK in a predetermined dividing ratio and outputs aclock signal CLK1, the frequency of which is lower than that of theclock signal CLK. The clock signal CLK 1 output from the dividingcircuit 162 is input to the jitter generation circuit 152. The jittergeneration circuit 152 adds a jitter to the clock signal CLK 1 from thedividing circuit 162 and supplies a clock signal GCLK 1 to the counter156, the timer 157 and the dividing circuit 163.

The dividing circuit 163 divides the clock signal GCLK 1 a predetermineddividing ratio and outputs a clock signal GCLK 2, the frequency of whichis lower than that of the clock signal GCLK 1. The clock signal GCLK 2is input to the parallel IO 158.

The CPU 153, the serial IO 154 and the RAM 155 in the semiconductordevice 151 operate at a high speed based on the clock signal CLK inputfrom the outside. The counter 156 and the timer 157 operate at a lowspeed based on the clock signal GCLK 1 to which a jitter is added.Moreover, the parallel IO 158 operates at a lower speed than that of thecounter 156 and the timer 157 based on the clock signal GCLK 2.

In other words, in the twenty-first embodiment, the second internalcircuit (counter 156, timer 157, parallel IO 158) is a circuit, theoperation speed of which is lower than that of the first internalcircuit (CPU 153, serial IO 154, RAM 55), and a jitter is added to theclock signals GCLK 1 and GCLK 2 for operating the second internalcircuit. In this case, the frequency of the clock signals GCLK 1 andGCLK 2 is lower than that of the clock signal CLK, therefore, it ispossible to add a larger amount of jitter. As a result, it is possibleto effectively reduce the radiation noise.

FIG. 63 is a diagram showing the configuration of the semiconductordevice 151 in the twenty-second embodiment. The same symbols are usedfor those which are the same as the configuration in the twenty-firstembodiment only the difference from the twenty-first embodiment isdescribed below.

The semiconductor device 151 in the twenty-second embodiment comprisestwo jitter generation circuits, that is, the jitter generation circuit152 and a jitter generation circuit 166, and is configured in such a waythat the amount of jitter to be added to the clock signal is changed inaccordance with the operation speed of the internal circuit.

To be exact, in the semiconductor device 151, the clock signal CLK 1output from the dividing circuit 162 is input to the dividing circuit163. The dividing circuit 163 divides the clock signal CLK 1 in apredetermined dividing ratio and outputs a CLK 2, the frequency of whichis lower than that of the clock signal CLK 1.

The jitter generation circuit 152 adds a jitter to the clock signal CLK1 from the dividing circuit 162 and supplies the clock signal GCLK 1 tothe counter 156 and the timer 157. On the other hand, the jittergeneration circuit 166 adds a jitter to the clock signal CLK 2 from thedividing circuit 163 and supplies the clock signal GCLK 2 to theparallel IO 158. The jitter generation circuit 166 adds a larger amountof jitter than that of the jitter generation circuit 152.

According to the semiconductor device 151, it is possible to add aproper jitter to the clock signals CLK1 and CLK2 in accordance with theoperation speed of the internal circuit. In this case, it is alsopossible to increase the proportion of the internal circuit whichoperates based on the clock signals GCLK1 and GCLK2 with a jitter added.As a result, it is possible to more effectively reduce the radiationnoise of the semiconductor device.

The twentieth to twenty-second embodiments can be modified as follows. Afunction for adjusting the amount of jitter in accordance with theoperation state of the internal circuit can be provided to the jittergeneration circuits 152 and 166 in the semiconductor device 151.

In concrete terms, a case where a function for adjusting the amount ofjitter is provided to the jitter generation circuit 151 in thetwenty-second embodiment is described below.

As shown in FIG. 64, the jitter generation circuit 152 in thesemiconductor device 151 includes a first generation section 152 a and asecond generation section 152 b and one of the generation sections 152 aand 152 b is activated based on a mode signal MODE output from theCPU153. In the jitter generation circuit 152, when the first generationsection 152 a is activated, a small jitter is added to the clock signalCLK and when the second generation section 152 b is activated, a largejitter is added to the clock signal CLK.

The operation mode of the semiconductor device 151 includes variousoperation modes such as a test mode, a sleep mode, a high-speedoperation mode, and a low-speed operation mode. The CPU153 judges theoperation mode from time to time and outputs a mode signal MODE inaccordance with the current operation mode. For example, when theoperation mode in the semiconductor device 151 changes from thehigh-speed operation mode to the low-speed operation mode, the modesignal MODE output from the CPU153 is reversed from the H level to the Llevel. Then, based on the mode signal MODE, the first generation section152 a in the jitter generation circuit 152 is deactivated and at thesame time the second generation section 152 b is activated. As a result,it is made possible to add a large jitter to the clock signal CLK.

As described above, by adjusting the amount of jitter in accordance withthe operation state of the semiconductor 151, it is possible toeffectively reduce the radiation noise of the semiconductor device 151.Moreover, by changing the amount of jitter based on a test mode signal,the test of the semiconductor device 151 can be conducted easily.

It is also possible to configure so that the amount of jitter isadjusted in accordance with the source voltage as in the semiconductordevice 151 shown in FIG. 65. In other words, the semiconductor device151 is provided with a source voltage monitoring circuit 159 whichmonitors the source voltage supplied to the circuits such as the CPU153,and a control signal CON in accordance with the level of the sourcevoltage is output from the source voltage monitoring circuit 159. Basedon the control signal CON, one of the generation sections 152 a and 152b is activated.

For example, when the source voltage falls below a predetermined value,the control signal CON is reversed from the L level to the H level.Then, based on the control signal CON, the first generation section 152a in the jitter generation circuit 152 is activated and at the same timethe second generation section 152 b is deactivated. As a result, it ismade possible to add a small jitter to the clock signal CLK. In otherwords, when the semiconductor device 151 operates in a low-voltagestate, the amount of jitter to be added to the clock signal CKL isreduced and when the semiconductor device 151 operates in a high-voltagestate, the amount of jitter to be added to the clock signal CKL isincreased.

When the semiconductor device 151 is set to a low-voltage state, theradiation noise is reduced and the operation speed-margin of the circuitis decreased. Because of this, it is possible to prevent a circuitmalfunction by reducing the amount of jitter. On the other hand, whenthe semiconductor device 151 is set to a high-voltage state, theradiation noise is increased and the operation speed margin of thecircuit is increased. Because of this, it is possible to effectivelyreduce the radiation noise by increasing the amount of jitter.

Moreover, it is also possible to configure in such a way that adetection circuit for detecting the frequency of the clock signal CLK isprovided in the semiconductor device 151 and the amount of jitter isadjusted based on the detection result. Still moreover, it is alsopossible to configure in such a way that the amount of jitter isadjusted based on information about the source voltage or the like whichthe CPU153 obtains.

The jitter generation circuit 152 in the semiconductor device 151comprises the two generation sections 152 a and 152 b and has aconfiguration in which the amount of jitter to be added to the clocksignal CLK is switched between two steps, but it is also possible toprovide a configuration which comprises three or more generationsections and in which the amount of jitter is switched between multiplesteps. A jitter generation circuit, in which the amount of jitter can beadjusted arbitrarily in accordance with a setting signal input from theoutside, has been put to practical use. When such a jitter generationcircuit is used, it is possible to configure in such a way that theamount of jitter is adjusted based on the setting signal in accordancewith each operation mode.

The semiconductor device 151 in the twenty-second embodiment comprisesthe two jitter generation circuits 152 and 166 and has a configurationin which two different jitters are added to the precise clock signalsCLK1 and CLK2 to which no jitter is added yet in each generationcircuit, but the configuration is not limited to this. For example, itis also possible to configure in such a way that to the clock signal towhich a jitter is added in the first jitter generation circuit 152, ajitter is further added in the second jitter generation circuit 166, asin the semiconductor device 151 shown in FIG. 66. In other words, thesecond jitter generation circuit 166 in the semiconductor device 151functions as a jitter increasing circuit for increasing the amount ofjitter to be added to a clock signal.

According to this semiconductor device, it is possible to reduce thecircuit scale of the second jitter generation circuit 166 compared tothe semiconductor device which generates a jitter independently of eachother. Moreover, it is also possible to make, without fail, the amountof jitter to be added to the clock signal GCLK1 for operating thecounter 156 and the timer 157 differ from the amount of jitter to beadded to the clock signal GCLK2 for operating the parallel IO158.

In the semiconductor device shown in FIG. 63 and FIG. 66, the two jittergeneration circuits 152 and 166 are provided, but it is also possible toprovide three or more jitter generation circuits.

1. A jitter generation circuit for inputting a reference input signalthe voltage level of which changes in a constant period and outputtingthe reference input signal after adding a jitter thereto, the jittergeneration circuit comprising a circuit for changing an output to afirst level or a second level in accordance with the reference inputsignal, wherein the circuit is formed so as to be capable of changingthe threshold voltage and an output signal with a jitter added is outputby changing the threshold voltage.
 2. A jitter generation circuit, asset forth in claim 1, wherein a hysteresis inverter circuit having thehysteresis characteristic, an inverter circuit not having the hysteresischaracteristic, and a switch circuit provided between an output terminalfor outputting the output signal and the hysteresis inverter circuit andbetween the output terminal and the inverter circuit respectively arecomprised and the switch circuit switches the connections so that eitherthe hysteresis inverter circuit or the inverter circuit is connected tothe output terminal.
 3. A jitter generation circuit, as set forth inclaim 1, wherein a hysteresis inverter circuit consisting of a pluralityof transistors and a switch for cutting off the transistors, which areprovided in order to confer hysteresis on the hysteresis invertercircuit, from the hysteresis inverter circuit are comprised.
 4. A jittergeneration circuit, as set forth in claim 1, wherein a plurality of gatecircuits with different threshold voltages are connected in parallel andany one of the gate circuits is selectively connected to the outputterminal by a switch circuit provided between an output terminal foroutputting the output signal and each gate circuit.
 5. A semiconductordevice comprising the jitter generation circuit set forth in claim 1 andan internal circuit which operates based on an output signal output fromthe jitter generation circuit.
 6. A semiconductor device, as set forthin claim 5, wherein a clock generation circuit for generating a clocksignal as the reference input signal and a circuit provided between theclock generation circuit and the jitter generation circuit and whichchanges the shape of the clock signal changing in a rectangular waveform to a sinusoidal wave form.
 7. A semiconductor device, as set forthin claim 5, wherein a clock generation circuit for generating a clocksignal as the reference input signal and a selection signal generationcircuit for generating a selection signal based on the reference inputsignal generated in the clock generation circuit are comprised and thethreshold voltages are switched by the selection signal.
 8. Asemiconductor device comprising the jitter generation circuit set forthin claim 1, a first internal circuit to which a clock signal to be aninput signal to the jitter generation circuit is supplied, and a secondinternal circuit the operation timing of which is less strict than thatof the first internal circuit and to which a clock signal with a jitteradded in the jitter generation circuit is supplied.
 9. A semiconductordevice comprising a jitter generation circuit for inputting a clocksignal and outputting the clock signal after adding a jitter thereto, afirst internal circuit to which a lock signal to be an input signal tothe jitter generation circuit is supplied, and a second internal circuitthe operation timing of which is less strict than that of the firstinternal circuit and to which a clock signal, with a jitter added in thejitter generation circuit, is supplied.
 10. A semiconductor device, asset forth in claim 8, wherein a dividing circuit is comprised forgenerating and inputting to the jitter generation circuit a second clocksignal, the frequency of which is lower than that of a first clocksignal, by dividing the first clock signal which is used to operate thefirst internal circuit.
 11. A semiconductor device, as set forth inclaim 8, wherein a plurality of the jitter generation circuits arecomprised and the amount of jitter to be added to a clock signal is madediffer from each other in each jitter generation circuit.
 12. Asemiconductor device, as set forth in claim 8, wherein the jittergeneration circuit has a function for adjusting the amount of jitter tobe added to a clock signal in accordance with the condition of operationof the internal circuit.
 13. A semiconductor device, as set forth inclaim 12, wherein the amount of jitter in the jitter generation circuitis adjusted in accordance with the power supply voltage to the internalcircuit.
 14. A semiconductor device, as set forth in claim 12, whereinthe amount of jitter in the generation circuit is adjusted in accordancewith the operation speed of the internal circuit.
 15. A semiconductordevice, as set forth in claim 11, wherein a first jitter generationcircuit for adding a jitter to a clock signal and a second jittergeneration circuit for further adding a jitter to the clock signal withthe jitter added are comprised.
 16. A semiconductor device, as set forthin claim 11, wherein a first jitter generation circuit and a secondjitter generation circuit to which a clock signal the frequency of whichis lower than the first jitter generation circuit is input are comprisedand the second jitter generation circuit adds a jitter larger than thatof the first jitter generation circuit.